Intel Stratix 10 User Manual

Bit Name Description SW Access
HW Access
Protection
Reset
3'b000 : Select EHIP Core TX Data - all lanes should have same
selection
3'b001 : Select EHIP Lane TX Data
3'b010 : Select AIB Lane TX Data with Deskew - should be same for all
lanes
3'b011 : Select AIB Lane TX Data No Deskew
3'b110 : FEC Lane Disabled - tie inputs to 0
3'b111 : Debug Mode - Select Loopback from output of RS-FEC RX
2:0 core_tx_in_sel0 RS-FEC TX Select For Lane 0
Indicates which data to select for rsfec core TX input
3'b000 : Select EHIP Core TX Data - all lanes should have same
selection
3'b001 : Select EHIP Lane TX Data
3'b010 : Select AIB Lane TX Data with Deskew - should be same for all
lanes
3'b011 : Select AIB Lane TX Data No Deskew
3'b110 : FEC Lane Disabled - tie inputs to 0
3'b111 : Debug Mode - Select Loopback from output of RS-FEC RX
RW
RO
-
0x0
9.5.3. rsfec_top_rx_cfg
Description Address Addressing Mode
RS-FEC TX configuration register 0x14 32-bits
The reset values in this table represents register values after a reset has completed.
Bit
Name Description SW Access
HW Access
Protection
Reset
31:28 loopback_tx2rx FEC RX Bypass
Setting this bit enable loopback from TX RS-FEC to RX RS-FEC instead of
getting from XcvrIf. This is one bit per lane [bit0=lane0]
RW
RO
-
0x0
13:12 core_rx_out_sel3 RS-FEC RX Output Select For Lane 3
Indicates which data to select for rsfec core TX input. All lanes should
have same selection for EHIP and RS-FEC_DIRECT_100G modes. Does
not work for TX Select of Elane and Loopback
2'b00 : Bypass RS-FEC RX paths - data from XCVRIF fec / pcs path
(normal bypass)
2'b01 : Select output of RS-FEC RX.
2'b10 : Bypass RS-FEC RX paths - data from XCVRIF fec path for both
ehip and elane
2'b11 : Debug Mode - Select Loopback from EHIP TX Data.
RW
RO
-
0x0
9:8 core_rx_out_sel2 RS-FEC RX Output Select For Lane 2
Indicates which data to select for rsfec core TX input. All lanes should
have same selection for EHIP and RS-FEC_DIRECT_100G modes. Does
not work for TX Select of Elane and Loopback
2'b00 : Bypass RS-FEC RX paths - data from XCVRIF fec / pcs path
(normal bypass)
2'b01 : Select output of RS-FEC RX.
2'b10 : Bypass RS-FEC RX paths - data from XCVRIF fec path for both
ehip and elane
RW
RO
-
0x0
continued...
9. Register Map
UG-20056 | 2019.02.04
Send Feedback
Intel
®
Stratix
®
10 E-Tile Transceiver PHY User Guide
195

Intel Stratix 10 Specifications

General

Brand	Intel
Model	Stratix 10
Category	Control Unit
Language	English