Intel Stratix 10 User Manual

Figure 89. Injecting Error Bits Using the PMA Attributes Through AVMM Registers
0x00 0x02 0x01 0x25
0x87 0x86 0x85 0x84
7 6 5 4 3 2 1 07 6 5 4 3 2 1 0
PMA code
address
PMA code
value
0x90
7 0 0 07 7
0x8B 0x8A
Request issue
to PMA:
enable or
disable
Status of
request
made to
PMA[0]
Status of
request
made to
PMA[7]
7 0 07
Error Inject
Table 58. PMA Attribute Code Error Inject Bits
Name Address Bit Range Description
Error Inject 0x001B 0x85[7:0], 0x84[7:0] Number of errors to inject
1. Set Error Injection for injecting single bit error.
a. Write 0x84[7:0] = 0x01.
b. Write 0x85[7:0] = 0x00.
c. Write 0x86[7:0] = 0x1B.
d. Write 0x87[7:0] = 0x00.
e. Write 0x90[0] = 1’b1.
f. Read 0x8A[7]. It should be 1.
g. Read 0x8B[0] until it changes to 0.
h. Write 0x8A[7] to 1'b1 to clear the 0x8A[7] value.
2. Set Error Injection for injecting burst of 10 bit errors.
a. Write 0x84[7:0] = 0x0A.
b. Write 0x85[7:0] = 0x00.
c. Write 0x86[7:0] = 0x1B.
d. Write 0x87[7:0] = 0x00.
e. Write 0x90[0] = 1’b1.
f. Read 0x8A[7]. It should be 1.
g. Read 0x8B[0] until it changes to 0.
h. Write 0x8A[7] to 1'b1 to clear the 0x8A[7] value.
8.4. PMA Receiver Equalization Adaptation Usage Model
The PMA receiver adaptive equalization engine allows the equalization blocks to adapt
to an optimal value. These optimal values can be read back.
8. Dynamic Reconfiguration Examples
UG-20056 | 2019.02.04
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Intel Stratix 10 Specifications

General

Brand	Intel
Model	Stratix 10
Category	Control Unit
Language	English