Intel Stratix 10 User Manual

6.8. Interfaces
6.8.1. Reset Parameters in the Native PHY GUI
Table 49. Reset Parameters
Parameter Name Range Description
Enable Manual Reset On/Off On = Use the manual reset process to reset the Native PHY.
Enable Fast Simulation
for Controller
On/Off On = Use reduced reset timings for simulation.
Enable Fast Simulation
for Sequencer
On/Off On = Use reduced reset timings for simulation.
Enable Individual TX
and RX Reset
On/Off On = Use individual reset to reset the TX or RX PMA path individually.
Use Separate TX/RX
Reset Per Channel
On/Off If you implement multiple channels in your Native PHY IP
• On = Each channel’s signals are independent from others and do not gate
other channels’ reset sequences.
•
Off = If any channel’s PMA is not ready, deasserting rx_is_lockedtodata
affects all channels.
If you implement a single channel in the Native PHY IP, this has no effect.
Enable TX/RX reset
sequencing
On/Off On = The reset controller deasserts the TX before deasserting the RX. This
parameter needs to be set when RS-FEC is enabled in aggregate mode and
enable datapath and interface reconfiguration is disabled.
RX Reset Duration 100 ns to 1
ms
The RX pulses the rx_is_lockedtodata output when there is no serial data.
The reset controller by default waits for the rx_is_lockedtodata to be high
for 180 μs before deasserting reset. You can set this parameter for additional
filtering.
6.8.2. HDL Ports/Interfaces
Table 50. HDL Ports/Interfaces when the Reset Controller is in Automatic Mode
Port Name Direction Width Description
reset
Input Number of
channels
Resets TX and RX when asserted. Visible when Enable individual TX
and RX resets is disabled. When the Native PHY is configured in PAM4
high datarate mode, the bus width equals the number of data channels
parameter in the GUI divided by two.
tx_reset
Input Number of
channels
Resets TX when asserted. Visible when Enable individual TX and RX
resets is enabled. When the Native PHY is configured in PAM4 high
datarate mode, the bus width equals the number of data channels
parameter in the GUI divided by two.
rx_reset
Input Number of
channels
Resets RX when asserted. Visible when Enable individual TX and RX
resets is enabled. When the Native PHY is configured in PAM4 high
datarate mode, the bus width equals the number of data channels
parameter in the GUI divided by two.
tx_ready
Output Number of
channels
Status signal to indicate when TX resets sequencing is complete.
Deasserts during TX reset assertion.
Asserts a few clock cycles after deassertion of TX resets.
rx_ready
Output Number of
channels
Status signal to indicate when RX resets sequencing is complete.
Deasserts during RX reset assertion.
continued...
6. Resetting Transceiver Channels
UG-20056 | 2019.02.04
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Intel
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Stratix
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10 E-Tile Transceiver PHY User Guide
117

Intel Stratix 10 Specifications

General

Brand	Intel
Model	Stratix 10
Category	Control Unit
Language	English