Intel Stratix 10 User Manual

2
31
–1 PRBS pattern This PRBS pattern
(7)
is based on the generator polynomial x
31
+
x
28
+ 1
For more details on Register Read/Write support and programming, refer to PMA
Register Map and PMA Attribute Codes to configure these parameters.
Related Information
• PMA Register Map on page 165
• PMA Attribute Codes on page 170
3.1.2. Receiver PMA
The receiver recovers the clock information from the received serial data, deserializes
the high-speed serial data and creates a parallel data stream for either the receiver
EHIP_LANE, EHIP_CORE, RS-FEC, or the FPGA core.
The receiver portion of the PMA consists of the receiver buffer, the clock data recovery
(CDR) unit, and the deserializer.
3.1.2.1. Receiver Buffer
The receiver buffer receives serial data from the input pins and feeds it to the clock
data recovery (CDR) unit and deserializer.
The receiver buffer supports the following features:
• Programmable termination mode
• Receiver equalization
For more details on Register Read/Write support and programming, refer to PMA
Register Map and PMA Attribute Codes to configure these parameters.
Related Information
• PMA Register Map on page 165
• PMA Attribute Codes on page 170
3.1.2.1.1. Programmable Termination Modes
Termination modes are programmable. However, the differential impedance values are
fixed (as per the Ethernet standard specifications).
The transceiver RX is AC-coupled on-chip. Therefore, no off-chip AC-coupling capacitor
is required as long as the RX input common mode is between AGND and VCCH_GXE
and the RX input amplitude is < 1200 mVp-p differential. For details, refer the Intel
Stratix 10 Device Family Pin Connection Guidelines.
For more details on Register Read/Write support and programming, refer to PMA
Register Map and PMA Attribute Codes to configure these parameters.
Related Information
• PMA Register Map on page 165
(7)
This polynomial generates data patterns whose run lengths are up to 31 1s or 30 0s in a row.
The pattern repeats every 2
31
–1 bits (approximately 2.15 Gbits).
3. Intel Stratix 10 E-Tile Transceiver PHY Architecture
UG-20056 | 2019.02.04
Intel
®
Stratix
®
10 E-Tile Transceiver PHY User Guide
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Intel Stratix 10 Specifications

General

Brand	Intel
Model	Stratix 10
Category	Control Unit
Language	English