Intel Stratix 10 User Manual

For more details on PRBS13Q pattern generation, refer to CEI-56G-VSR-PAM4
specifications. On similar lines, the PRBS31Q pattern is a repeating 2
31
-1 symbols
long, formed by gray coding and PAM4 encoding of the PRBS31 pattern. This pattern is
used for receiver testing.
Note: Gray encoding is enabled by default in PAM4 patterns.
Table 28. Supported Programmable NRZ and PAM4 Patterns
NRZ Mode PAM4 Mode
PRBS7 PRBS7Q
PRBS9 PRBS9Q
PRBS11 PRBS11Q
PRBS13 PRBS13Q
PRBS15 PRBS15Q
PRBS23 PRBS23Q
PRBS31 PRBS31Q
User-defined 80-bit Pattern
More details on these patterns are as follows:
2
7
–1 PRBS pattern This standard PRBS pattern
(4)
is based on the generator
polynomial x
7
+ x
6
+ 1 (refer to ITU V.29)
2
9
–1 PRBS pattern This PRBS pattern is based on the generator polynomial x
9
+ x
5
+ 1 (refer to CCITT O.151/ITU-T O.151)
2
11
–1 PRBS pattern This PRBS pattern is based on the generator polynomial x
11
+
x
9
+ 1 (refer to CCITT O.151/ITU-T O.151)
2
13
–1 PRBS pattern This PRBS pattern is based on the generator polynomial x
13
+
x
12
+ x
2
+ x + 1 (refer to CCITT O.151/ITU-T O.151)
2
15
–1 PRBS pattern This PRBS pattern
(5)
is based on the generator polynomial x
15
+ x
14
+ 1 (refer to CCITT O.151/ITU-T O.151)
2
23
–1 PRBS pattern This PRBS pattern
(6)
is based on the generator polynomial x
23
+
x
18
+ 1 (refer to CCITT O.151/ITU-T O.151)
(4)
This pattern repeats every 127 bits and you can use it with a PRBS receiver to facilitate
loopback testing. This pattern facilitates the testing of chip-to-chip communications with other
transceiver channel TX/RX Macro receivers on external chips or be fed to instruments such as a
bit error rate tester (BERT).
(5)
This polynomial provides a data pattern that is more challenging for clock and data recovery
circuits. Run lengths up to 15 1s or 14 0s in a row are embedded in the pattern. The pattern
repeats every 2
15
–1 bits (approximately 32.8 Kb).
(6)
This polynomial provides a data pattern that is more challenging for clock and data recovery
circuits. Run lengths up to 23 1s or 22 0s in a row are embedded in the pattern. The pattern
repeats every 2
23
–1 bits (approximately 8.4 Mbits).
3. Intel Stratix 10 E-Tile Transceiver PHY Architecture
UG-20056 | 2019.02.04
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10 E-Tile Transceiver PHY User Guide
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Intel Stratix 10 Specifications

General

Brand	Intel
Model	Stratix 10
Category	Control Unit
Language	English