Intel Stratix 10 User Manual

Ratio
Supported Above 15
Gbaud per Second
1/2 Rate 1/4 Rate 1/8 Rate
146 Yes Yes No No
148 Yes Yes Yes No
150 Yes Yes No No
152 Yes Yes Yes Yes
154 Yes Yes No No
155 Yes No No No
156 Yes Yes Yes No
158 Yes Yes No No
160 Yes Yes Yes Yes
162 Yes Yes No No
164 Yes Yes Yes No
165 Yes No No No
166 Yes Yes No No
168 Yes Yes Yes Yes
170 Yes Yes No No
172 Yes Yes Yes No
174 Yes Yes No No
175 Yes No No No
176 Yes Yes Yes Yes
178 Yes Yes No No
180 Yes Yes Yes No
9.5. RS-FEC Registers
The delay between RS-FEC register reads should be at least 10 μs.
Table 63. RS-FEC Registers
Address Name Description Reset
0x04 rsfec_top_clk_cfg RS-FEC Clock configuration register 0x0000 0F00
0x10 rsfec_top_tx_cfg RS-FEC TX configuration register 0x0000 0000
0x14 rsfec_top_rx_cfg RS-FEC RX configuration register 0x0000 0000
0x20 tx_aib_dsk_conf Defines the configuration fields for TX Deskew 0x0000 0000
0x30 rsfec_core_cfg RS-FEC core configuration 0x0000 0000
0x40 rsfec_lane_cfg_0 RS-FEC per lane configuration 0x0000 0000
0x44 rsfec_lane_cfg_1
0x48 rsfec_lane_cfg_2
0x4C rsfec_lane_cfg_3
continued...
9. Register Map
UG-20056 | 2019.02.04
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Intel Stratix 10 Specifications

General

Brand	Intel
Model	Stratix 10
Category	Control Unit
Language	English