Intel Stratix 10 User Manual

Bit Name Description SW Access
HW Access
Protection
Reset
Not valid when transcoding is bypassed. W1S
-
0 hdr_inv PCS Tx 66b invalid sync header.
Not valid when transcoding is bypassed.
W1C
W1S
-
0x0
9.5.11. rsfec_lane_tx_inten
Register Name Description Address Addressing Mode
rsfec_lane_tx_inten_0 RS-FEC per lane TX status hold interrupt - set to 1 to
enable rsfec_lane_tx lane interrupt
0x140 32-bits
rsfec_lane_tx_inten_1 0x144
rsfec_lane_tx_inten_2 0x148
rsfec_lane_tx_inten_3 0x14C
The reset values in this table represents register values after a reset has completed.
Bit Name Description SW Access
HW Access
Protection
Reset
3 pace_inv PCS TX pacing violation.
When RSFEC_LANE_CFG.rs544 = 0 .pace_inv is never set.
When RSFEC_LANE_CFG.rs544 = 1 .pace_inv is set when there is more than 33
consecutive non-idle cycles.
RW
RO
-
0x0
2 resync PCS TX alignment/codeword marker resync.
Not valid when RSFEC_LANE_CFG1.eng_cust_am_en = 1.
RW
RO
-
0x0
1 blk_inv PCS TX 66b invalid block type.
Not valid when transcoding is bypassed.
RW
RO
-
0x0
0 hdr_inv PCS TX 66b invalid sync header.
Not valid when transcoding is bypassed.
RW
RO
-
0x0
9.5.12. rsfec_lane_rx_stat
Register Name
Description Address Addressing Mode
rsfec_lane_rx_stat_0 RS-FEC per lane RX status 0x150 32-bits
rsfec_lane_rx_stat_1 0x154
rsfec_lane_rx_stat_2 0x158
rsfec_lane_rx_stat_3 0x15C
9. Register Map
UG-20056 | 2019.02.04
Intel
®
Stratix
®
10 E-Tile Transceiver PHY User Guide
Send Feedback
200

Intel Stratix 10 Specifications

General

Brand	Intel
Model	Stratix 10
Category	Control Unit
Language	English