Intel Stratix 10 User Manual

9.5.9. rsfec_lane_tx_stat
Register Name Description Address Addressing Mode
rsfec_lane_tx_stat_0 RS-FEC per lane TX status 0x120 32-bits
rsfec_lane_tx_stat_1 0x124
rsfec_lane_tx_stat_2 0x128
rsfec_lane_tx_stat_3 0x12C
The reset values in this table represents register values after a reset has completed.
Bit Name Description SW Access
HW Access
Protection
Reset
3 pace_inv PCS TX pacing violation.
With RS528 .pace_inv is never set.
With RS544 .pace_inv is set when the layer above presents TX data in more than 33
consecutive cycles.
RO
WO
-
0x0
2 resync PCS TX alignment/codeword marker resync.
Not valid when RS-FEC_LANE_CFG1.eng_cust_am_en = 1.
RO
WO
-
0x0
1 blk_inv PCS TX 66b invalid block type.
Not valid when transcoding is bypassed.
RO
WO
-
0x0
0 hdr_inv PCS TX 66b invalid sync header.
Not valid when transcoding is bypassed.
RO
WO
-
0x0
9.5.10. rsfec_lane_tx_hold
Register Name
Description Address Addressing Mode
rsfec_lane_tx_hold_0 RS-FEC per lane TX status hold 0x130 32-bits
rsfec_lane_tx_hold_1 0x134
rsfec_lane_tx_hold_2 0x138
rsfec_lane_tx_hold_3 0x13C
The reset values in this table represents register values after a reset has completed.
Bit
Name Description SW Access
HW Access
Protection
Reset
3 pace_inv PCS TX pacing violation.
With RS528 .pace_inv is never set.
With RS544 .pace_inv is set when the layer above presents TX data in more than 33
consecutive cycles.
W1C
W1S
-
0x0
2 resync PCS Tx alignment/codeword marker resync.
Not valid when RSFEC_LANE_CFG1.eng_cust_am_en = 1.
W1C
W1S
-
0x0
1 blk_inv PCS Tx 66b invalid block type. W1C 0x0
continued...
9. Register Map
UG-20056 | 2019.02.04
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10 E-Tile Transceiver PHY User Guide
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Intel Stratix 10 Specifications

General

Brand	Intel
Model	Stratix 10
Category	Control Unit
Language	English