Intel Stratix 10 User Manual

9.5.26. rsfec_uncorr_cw_cnt (Low)
Register Name Description Address Addressing Mode
rsfec_uncorr_cw_cnt_0_lo RS-FEC number of FEC codewords that could
not be corrected due to too many errors (low
word: bits 31 to 0)
0x220 32-bits
rsfec_uncorr_cw_cnt_1_lo 0x228
rsfec_uncorr_cw_cnt_2_lo 0x230
rsfec_uncorr_cw_cnt_3_lo 0x238
The reset values in this table represents register values after a reset has completed.
Bit Name Description SW Access
HW Access
Protection
Reset
31:0 stat Statistics value. RO
WO
-
0x0000 0000
9.5.27. rsfec_uncorr_cw_cnt (High)
Register Name Description Address Addressing Mode
rsfec_uncorr_cw_cnt_0_hi RS-FEC number of FEC codewords that could not be
corrected due to too many errors (high word: bits
63 to 32)
0x224 32-bits
rsfec_uncorr_cw_cnt_1_hi 0x22C
rsfec_uncorr_cw_cnt_2_hi 0x234
rsfec_uncorr_cw_cnt_3_hi 0x23C
The reset values in this table represents register values after a reset has completed.
Bit
Name Description SW Access
HW Access
Protection
Reset
31:0 stat Statistics value. RO
WO
-
0x0000 0000
9.5.28. rsfec_corr_syms_cnt (Low)
Register Name
Description Address Addressing Mode
rsfec_corr_syms_cnt_0_lo RS-FEC number of 10b symbols corrected for the
lane (low word: bits 31 to 0)
0x240 32-bits
rsfec_corr_syms_cnt_1_lo 0x248
rsfec_corr_syms_cnt_2_lo 0x250
rsfec_corr_syms_cnt_3_lo 0x258
The reset values in this table represents register values after a reset has completed.
Bit
Name Description SW Access
HW Access
Protection
Reset
31:0 stat Statistics value. RO 0x0000 0000
9. Register Map
UG-20056 | 2019.02.04
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Intel Stratix 10 Specifications

General

Brand	Intel
Model	Stratix 10
Category	Control Unit
Language	English