Intel Stratix 10 User Manual

Address Name Description Reset
0x244 rsfec_corr_syms_cnt_0_hi RS-FEC number of 10b symbols corrected for the lane (high word:
bits 63 to 32)
0x0000 0000
0x24C rsfec_corr_syms_cnt_1_hi
0x254 rsfec_corr_syms_cnt_2_hi
0x25C rsfec_corr_syms_cnt_3_hi
0x260 rsfec_corr_0s_cnt_0_lo RS-FEC number of bits corrected 0->1 for the lane (low word: bits
31 to 0)
0x0000 0000
0x268 rsfec_corr_0s_cnt_1_lo
0x270 rsfec_corr_0s_cnt_2_lo
0x278 rsfec_corr_0s_cnt_3_lo
0x264 rsfec_corr_0s_cnt_0_hi RS-FEC number of bits corrected 0->1 for the lane (high word: bits
63 to 32)
0x0000 0000
0x26C rsfec_corr_0s_cnt_1_hi
0x274 rsfec_corr_0s_cnt_2_hi
0x27C rsfec_corr_0s_cnt_3_hi
0x280 rsfec_corr_1s_cnt_0_lo RS-FEC number of bits corrected 1->0 for the lane (low word: bits
31 to 0)
0x0000 0000
0x288 rsfec_corr_1s_cnt_1_lo
0x290 rsfec_corr_1s_cnt_2_lo
0x298 rsfec_corr_1s_cnt_3_lo
0x284 rsfec_corr_1s_cnt_0_hi RS-FEC number of bits corrected 1->0 for the lane (high word: bits
63 to 32)
0x0000 0000
0x28C rsfec_corr_1s_cnt_1_hi
0x294 rsfec_corr_1s_cnt_2_hi
0x29C rsfec_corr_1s_cnt_3_hi
All statistic registers are 64 bits, and you must do two 32-bit reads. Intel recommends
that you enable the shadow_req[3:0] in offset address 0x108 explained in
rsfec_debug_cfg before reading the statistics register and disable after reading it.
Related Information
rsfec_debug_cfg on page 198
9.5.1. rsfec_top_clk_cfg
Description
Address Addressing Mode
RS-FEC Clock configuration register 0x4 32-bits
The reset values in this table represents register values after a reset has completed.
Bit
Name Description SW Access
HW Access
Protection
Reset
11:8 fec_lane_ena Rsfec Clock/Lane Enable RW
RO
-
0xF
continued...
9. Register Map
UG-20056 | 2019.02.04
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10 E-Tile Transceiver PHY User Guide
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Intel Stratix 10 Specifications

General

Brand	Intel
Model	Stratix 10
Category	Control Unit
Language	English