Intel Stratix 10 User Manual

Address Name Description Reset
0x1B8 rsfec_ln_skew_rx_2
0x1BC rsfec_ln_skew_rx_3
0x1C0 rsfec_cw_pos_rx_0 RS-FEC codeword bit position on RX 0x0000 0000
0x1C4 rsfec_cw_pos_rx_1
0x1C8 rsfec_cw_pos_rx_2
0x1CC rsfec_cw_pos_rx_3
0x1D0 rsfec_core_ecc_hold RS-FEC SRAM ECC status hold 0x0000 0000
0x1E0 rsfec_err_inj_tx_0 RS-FEC error injection mode 0x0000 0000
0x1E4 rsfec_err_inj_tx_1
0x1E8 rsfec_err_inj_tx_2
0x1EC rsfec_err_inj_tx_3
0x1F0 rsfec_err_val_tx_0 RS-FEC per lane error injection status 0x0000 0000
0x1F4 rsfec_err_val_tx_1
0x1F8 rsfec_err_val_tx_2
0x1FC rsfec_err_val_tx_3
0x200 rsfec_corr_cw_cnt_0_lo RS-FEC number of FEC codewords with errors that were corrected
(low word: bits 31 to 0)
0x0000 0000
0x208 rsfec_corr_cw_cnt_1_lo
0x210 rsfec_corr_cw_cnt_2_lo
0x218 rsfec_corr_cw_cnt_3_lo
0x204 rsfec_corr_cw_cnt_0_hi RS-FEC number of FEC codewords with errors that were corrected
(high word: bits 63 to 32)
0x0000 0000
0x20C rsfec_corr_cw_cnt_1_hi
0x214 rsfec_corr_cw_cnt_2_hi
0x21C rsfec_corr_cw_cnt_3_hi
0x220 rsfec_uncorr_cw_cnt_0_lo RS-FEC number of FEC codewords that could not be corrected due to
too many errors (low word: bits 31 to 0)
0x0000 0000
0x228 rsfec_uncorr_cw_cnt_1_lo
0x230 rsfec_uncorr_cw_cnt_2_lo
0x238 rsfec_uncorr_cw_cnt_3_lo
0x224 rsfec_uncorr_cw_cnt_0_hi RS-FEC number of FEC codewords that could not be corrected due to
too many errors (high word: bits 63 to 32)
0x0000 0000
0x22C rsfec_uncorr_cw_cnt_1_hi
0x234 rsfec_uncorr_cw_cnt_2_hi
0x23C rsfec_uncorr_cw_cnt_3_hi
0x240 rsfec_corr_syms_cnt_0_lo RS-FEC number of 10b symbols corrected for the lane (low word:
bits 31 to 0)
0x0000 0000
0x248 rsfec_corr_syms_cnt_1_lo
0x250 rsfec_corr_syms_cnt_2_lo
0x258 rsfec_corr_syms_cnt_3_lo
continued...
9. Register Map
UG-20056 | 2019.02.04
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10 E-Tile Transceiver PHY User Guide
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Intel Stratix 10 Specifications

General

Brand	Intel
Model	Stratix 10
Category	Control Unit
Language	English