Intel Stratix 10 User Manual

tx_pma_ready output is asserted before asserting/deasserting the
tx_pmaif_reset, tx_rsfec_reset, tx_aib_reset, or rsfec_reset inputs.
Ensure that you assert the rx_pma_ready output before asserting or deasserting the
rx_pmaif_reset, rx_rsfec_reset, or rx_aib_reset inputs.
Figure 73. RX Reset Timing Waveform
rx_pma_ready
rx_aib_reset
rx_pmaif_reset
rx_rsfec_reset
AVMM
rx_transfer_ready
Reset and reconfigure PMA
using PMA attribute codes
rx_is_lockedtodata
Figure 74. TX Reset Timing Waveform
tx_pma_ready
tx_aib_reset
rsfec_reset
tx_rsfec_reset
tx_pmaif_reset
AVMM
tx_transfer_ready
Reset and reconfigure PMA
using PMA attribute codes
Min 100 ns
Min 100 ns
Min 100 ns
Min 100 ns
6.6. Intel Quartus Prime Instantiated Transceiver Reset Sequencer
Intel Quartus Prime auto-infers the Master TRS during synthesis and auto-connects
the Master TRS to the Local TRS using the debug fabric master end-point to slave end-
point auto-connect technology.
Benefits
No intervention – The designer does not need to expose every reset request and
acknowledge port on the interfaces of the design modules to be connected to the
Master TRS.
6. Resetting Transceiver Channels
UG-20056 | 2019.02.04
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10 E-Tile Transceiver PHY User Guide
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Intel Stratix 10 Specifications

General

Brand	Intel
Model	Stratix 10
Category	Control Unit
Language	English