Intel Stratix 10 User Manual

Bit Name Description SW Access
HW Access
Protection
Reset
-
7:0 inj0s Number of bits (modulo 256) that were changed from 1 to 0 on each physical lane.
Cleared when the corresponding RSFEC_ERR_INJ_TX.rate is written with a non-zero
value after being all zero, i.e. when a test is initiated. A value read from this register is
not reliable while injecting. A value read is reliable when the test is completed, i.e.
after the lane's RSFEC_ERR_INJ_TX.rate or RSFEC_ERR_INJ_TX.pat has been cleared.
One entry per physical lane, regardless of RSFEC_CORE_CFG.frac.
RO
WO
-
0x00
9.5.24. rsfec_corr_cw_cnt (Low)
Register Name Description Address Addressing Mode
rsfec_corr_cw_cnt_0_lo RS-FEC number of FEC codewords with
errors that were corrected (low word: bits
31 to 0)
0x200 32-bits
rsfec_corr_cw_cnt_1_lo 0x208
rsfec_corr_cw_cnt_2_lo 0x210
rsfec_corr_cw_cnt_3_lo 0x218
The reset values in this table represents register values after a reset has completed.
Bit Name Description SW Access
HW Access
Protection
Reset
31:0 stat Statistics value. RO
WO
-
0x0000 0000
9.5.25. rsfec_corr_cw_cnt (High)
Description
Address Addressing Mode
rsfec_corr_cw_cnt_0_h
i
RS-FEC number of FEC codewords with errors
that were corrected (high word: bits 63 to 32)
0x204 32-bits
rsfec_corr_cw_cnt_1_h
i
0x20C
rsfec_corr_cw_cnt_2_h
i
0x214
rsfec_corr_cw_cnt_3_h
i
0x21C
The reset values in this table represents register values after a reset has completed.
Bit
Name Description SW Access
HW Access
Protection
Reset
31:0 stat Statistics value. RO
WO
-
0x0000 0000
9. Register Map
UG-20056 | 2019.02.04
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10 E-Tile Transceiver PHY User Guide
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Intel Stratix 10 Specifications

General

Brand	Intel
Model	Stratix 10
Category	Control Unit
Language	English