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Intel Stratix 10 User Manual

Intel Stratix 10
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Switching Reference Clocks on page 129
6.5. High Level Specification
The overall E-Tile reset sequencing solution consists of Reset Controller, a Master
Transceiver Reset Sequencer (Master TRS) and multiple Local Transceiver Reset
Sequencers (Local TRS or LTRS).
The Reset Controller is used to ensure proper timing requirements and
interconnections. It takes the reset signals and handles the assertion and deassertion
of TX reset and RX reset to Local TRS. It also gives the option to enable and disable
independent TX and RX reset, enable and disable independent channel reset and
provides fast simulation support.
A Master TRS services the reset requests from multiple Local TRS in a round-robin
fashion. Upon detecting a reset event (assertion or deassertion) on the reset signal,
the Local TRS raises a reset request to the Master TRS and waits for the reset
acknowledgment from the Master TRS. When it receives acknowledgment, the Local
TRS sends the reset event to the transceiver channels. If required, the Local TRS
sequences the actual reset signals that go to the channels and adds extra delays to
the reset assertion or deassertion. After the Local TRS is done with the reset, it drops
the reset request; then the Master TRS moves to the next Local TRS request.
There are two variants of Local TRS – TX LTRS and RX LTRS. The TX LTRS services the
TX reset signal, and the RX LTRS services RX reset signal. The Master ensures that a
characterized minimum separation time is honored between the reset
acknowledgments of any two reset requests across the device, ensuring the minimum
separation time between the reset events of any two reset signals across the device.
The Local TRS provides more delay if required by the reset signal.
6.5.1. Automatic Reset Mode
Figure 60. Reset Block Diagram with Single Reset Control
E-Tile Native PHY IP
Reset Controller
(Local TRS)
RS-FEC
EMIB
PMA Interface
Master TRS
Request
reset
tx_ready
rx_ready
Acknowledgement
6. Resetting Transceiver Channels
UG-20056 | 2019.02.04
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Intel
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10 E-Tile Transceiver PHY User Guide
105

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Intel Stratix 10 Specifications

General IconGeneral
BrandIntel
ModelStratix 10
CategoryControl Unit
LanguageEnglish

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