Intel Stratix 10 User Manual

Figure 61. Reset Block Diagram with Independent TX and RX Reset Controls
The reset controller can be subdivided into TX and RX reset controllers. This allows you to reset the TX or RX
independently.
E-Tile Native PHY IP
Reset Controller
(Local TRS)
RS-FEC
EMIB
PMA Interface
Master TRS
Request
tx_reset
tx_ready
rx_ready
Acknowledgement
TX
RX
rx_reset
Figure 62. TX Reset Sequence in Automatic Mode After Power-Up
tx_reset (1)
tx_pma_ready
(if PMA is reset/configured)
Note:
1. If you used the AVMM bus to reconfigure the RS-FEC/EMIB/PMAIF, you must assert tx_reset until
the RS-FEC/EMIB/PMAIF registers are written.
tx_ready
Use the AVMM bus to reset/reconfigure the PMA or
reconfigure RS-FEC/EMIB/PMAIF (optional)
Figure 63. RX Reset Sequence in Automatic Mode After Power-Up
rx_reset (1)
rx_pma_ready
(if PMA is reset/configured)
rx_ready
Use the AVMM bus to reset/reconfigure the
PMA or reconfigure RS-FEC/EMIB/PMAIF (optional)
rx_is_lockedtodata
Note:
1. If you used the AVMM bus to reconfigure the RS-FEC/EMIB/PMAIF, you must assert rx_reset
until the RS-FEC/EMIB/PMAIF registers are written.
6. Resetting Transceiver Channels
UG-20056 | 2019.02.04
Intel
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Stratix
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10 E-Tile Transceiver PHY User Guide
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Intel Stratix 10 Specifications

General

Brand	Intel
Model	Stratix 10
Category	Control Unit
Language	English