Intel Stratix 10 User Manual

2.2.3.3. RX Clock Options
Table 15. RX Clock Options
Parameter Range Description
Selected rx_clkout
clock source
Full-rate, half-
rate, div66
Specifies the clock source for the rx_clkout output clock.
Enable rx_clkout2
port
On/Off
Enables the optional rx_clkout2 output clock enabling the rx_clkout2
port.
Selected
rx_clkout2 clock
source
Full-rate, half-
rate, div66
Specifies the clock source for the rx_clkout2 output clock.
Selected
rx_coreclkin clock
network
Dedicated Clock
Global Clock
Specifies the type of clock network to route the clock signal to the
rx_coreclkin port. Dedicated Clock allows a higher maximum frequency
(fmax) between the FPGA core and the transceiver. The number of dedicated
clock lines are limited.
2.2.4. PMA Interface
PMA interface options are related to the interface of PMA side of the bridge between
the PMA and the FPGA core, the FEC module, and so on.
Figure 20. PMA Interface Options
Related Information
Physical Medium Attachment (PMA) Architecture on page 57
2. Implementing the Transceiver PHY Layer in Intel Stratix 10 Devices
UG-20056 | 2019.02.04
Intel
®
Stratix
®
10 E-Tile Transceiver PHY User Guide
Send Feedback
36

Intel Stratix 10 Specifications

General

Brand	Intel
Model	Stratix 10
Category	Control Unit
Language	English