Intel Stratix 10 - Default Chapter; Table of Contents

Contents
1. Intel
®
Stratix
®
10 E-Tile Transceiver PHY Overview....................................................... 7
1.1. Supported Features............................................................................................... 7
1.2. E-Tile Layout in Stratix 10 Device Variants................................................................ 8
1.2.1. Intel Stratix 10 TX H-Tile and E-Tile Configurations.........................................8
1.2.2. Stratix 10 MX H-Tile and E-Tile Configurations..............................................10
1.3. Transceiver Counts in Stratix 10 TX/MX Devices....................................................... 10
1.4. E-Tile Building Blocks........................................................................................... 11
1.4.1. GXE Transceiver Channel.......................................................................... 12
1.4.2. GXE Channel Usage..................................................................................13
1.4.3. Reference Clocks..................................................................................... 15
1.4.4. Ethernet Hard IP (EHIP)............................................................................19
1.4.5. Supported Applications/Modes................................................................... 21
1.4.6. Feature Comparison Between Transceiver Tiles.............................................21
1.5. Intel Stratix 10 E-Tile Transceiver PHY Overview Revision History............................... 22
2. Implementing the Transceiver PHY Layer in Intel Stratix 10 Devices........................... 24
2.1. Transceiver Design Flow in the Native PHY IP Core....................................................24
2.1.1. E-Tile Native PHY IP Core.......................................................................... 25
2.2. Configuring the Native PHY IP Core........................................................................ 25
2.2.1. General and Datapath Parameters.............................................................. 27
2.2.2. PMA Parameters...................................................................................... 29
2.2.3. Core Interface Options..............................................................................33
2.2.4. PMA Interface..........................................................................................36
2.2.5. PMA Adaptation....................................................................................... 37
2.2.6. Reed Solomon Forward Error Correction (RS-FEC) Parameters........................41
2.2.7. Reset Parameters.....................................................................................45
2.2.8. Dynamic Reconfiguration Parameters..........................................................46
2.2.9. Port Information...................................................................................... 49
2.2.10. PLL Mode.............................................................................................. 52
2.3. Implementing the Transceiver PHY Layer in Intel Stratix 10 Devices Revision History.... 54
3. Intel Stratix 10 E-Tile Transceiver PHY Architecture..................................................... 56
3.1. Physical Medium Attachment (PMA) Architecture...................................................... 57
3.1.1. Transmitter PMA...................................................................................... 59
3.1.2. Receiver PMA.......................................................................................... 64
3.1.3. PMA Tuning............................................................................................. 68
3.1.4. Loopback modes......................................................................................74
3.1.5. PMA Interface..........................................................................................76
3.1.6. TX PMA Bonding...................................................................................... 77
3.1.7. Unused Transceiver Channel...................................................................... 79
3.2. Physical Coding Sublayer (PCS) Architecture............................................................79
3.3. Reed Solomon Forward Error Correction (RS-FEC) Architecture.................................. 79
3.3.1. RS-FEC Modes......................................................................................... 80
3.4. Intel Stratix 10 E-Tile Transceiver PHY Architecture Revision History........................... 85
4. Clock Network...............................................................................................................86
4.1. Reference Clock Pins............................................................................................ 86
4.1.1. QSF Assignments for Reference Clock Pins...................................................89
Contents
Intel
®
Stratix
®
10 E-Tile Transceiver PHY User Guide
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