Intel Stratix 10 User Manual

4.2. Core Clock Network Use Case................................................................................ 89
4.2.1. Single 25 Gbps PMA Direct Channel (with FEC) Within a Single FEC Block........ 90
4.2.2. Single 10 Gbps PMA Direct Channel (without FEC)........................................ 90
4.2.3. Four 25 Gbps PMA Direct Channel (with FEC) within a Single FEC Block........... 91
4.2.4. PMA Direct 25 Gbps x 4 (FEC Off).............................................................. 94
4.2.5. PMA Direct 10.3125 Gbps x 4.................................................................... 95
4.2.6. PMA Direct 100GE Gbps (25 Gbps x 4 per lane) (FEC On).............................. 95
4.3. Clock Network Revision History..............................................................................97
5. PMA Calibration............................................................................................................ 98
5.1. PMA Calibration Revision History............................................................................ 99
6. Resetting Transceiver Channels.................................................................................. 100
6.1. When Is Reset Required?.................................................................................... 100
6.2. How Do I Reset?................................................................................................ 100
6.2.1. Resetting the Intel Stratix 10 E-Tile Transceiver..........................................101
6.2.2. Selecting the Reset Controller's Clock Source............................................. 102
6.3. Reset Block Architecture..................................................................................... 102
6.4. PMA Analog Reset.............................................................................................. 104
6.5. High Level Specification...................................................................................... 105
6.5.1. Automatic Reset Mode............................................................................ 105
6.5.2. Manual Reset Mode................................................................................ 107
6.5.3. Reset Controller Bypass.......................................................................... 112
6.6. Intel Quartus Prime Instantiated Transceiver Reset Sequencer..................................114
6.7. Block Diagrams..................................................................................................115
6.8. Interfaces......................................................................................................... 117
6.8.1. Reset Parameters in the Native PHY GUI....................................................117
6.8.2. HDL Ports/Interfaces.............................................................................. 117
6.9. Resetting Transceiver Channels Revision History..................................................... 118
7. Dynamic Reconfiguration............................................................................................ 119
7.1. Dynamically Reconfiguring Channel Blocks.............................................................120
7.2. Interacting with the Dynamic Reconfiguration Interface........................................... 120
7.3. Unsupported Features.........................................................................................121
7.4. Reading from the Dynamic Reconfiguration Interface.............................................. 121
7.5. Writing to the Dynamic Reconfiguration Interface.................................................. 122
7.6. Multiple Reconfiguration Profiles...........................................................................123
7.6.1. Reconfiguration Files...............................................................................124
7.6.2. Embedded Reconfiguration Streamer........................................................ 125
7.7. Arbitration.........................................................................................................126
7.8. Recommendations for PMA Dynamic Reconfiguration...............................................127
7.9. Steps to Perform Dynamic Reconfiguration............................................................ 127
7.10. PMA Attribute Details........................................................................................ 129
7.11. Dynamic Reconfiguration Flow for Special Cases................................................... 129
7.11.1. Switching Reference Clocks....................................................................129
7.12. Ports and Parameters........................................................................................131
7.13. Embedded Debug Features................................................................................ 135
7.13.1. Altera Debug Master Endpoint (ADME).....................................................135
7.13.2. Optional Dynamic Reconfiguration Logic.................................................. 136
7.14. Timing Closure Recommendations...................................................................... 136
7.15. Transceiver Register Map...................................................................................137
7.16. Loading IP Configuration Settings....................................................................... 137
Contents
Send Feedback
Intel
®
Stratix
®
10 E-Tile Transceiver PHY User Guide
3

Intel Stratix 10 Specifications

General

Brand	Intel
Model	Stratix 10
Category	Control Unit
Language	English