Intel Stratix 10 User Manual

Bit Name Description SW Access
HW Access
Protection
Reset
WO
-
9.5.29. rsfec_corr_syms_cnt (High)
Register Name Description Address Addressing Mode
rsfec_corr_syms_cnt_0_hi RS-FEC number of 10b symbols corrected for the
lane (high word: bits 63 to 32)
0x244 32-bits
rsfec_corr_syms_cnt_1_hi 0x24C
rsfec_corr_syms_cnt_2_hi 0x254
rsfec_corr_syms_cnt_3_hi 0x25C
The reset values in this table represents register values after a reset has completed.
Bit Name Description SW Access
HW Access
Protection
Reset
31:0 stat Statistics value. RO
WO
-
0x0000 0000
9.5.30. rsfec_corr_0s_cnt (Low)
Register Name
Description Address Addressing
Mode
rsfec_corr_0s_cnt_0_lo RS-FEC number of bits corrected 0->1 for the lane
(low word: bits 31 to 0)
0x260 32-bits
rsfec_corr_0s_cnt_1_lo 0x268
rsfec_corr_0s_cnt_2_lo 0x270
rsfec_corr_0s_cnt_3_lo 0x278
The reset values in this table represents register values after a reset has completed.
Bit
Name Description SW Access
HW Access
Protection
Reset
31:0 stat Statistics value. RO
WO
-
0x0000 0000
9. Register Map
UG-20056 | 2019.02.04
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10 E-Tile Transceiver PHY User Guide
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Intel Stratix 10 Specifications

General

Brand	Intel
Model	Stratix 10
Category	Control Unit
Language	English