Intel Stratix 10 User Manual

4.2.4. PMA Direct 25 Gbps x 4 (FEC Off)
This use case does not include FEC; therefore, there is no need for clock sharing
between the four 25-Gbps channels.
For FIFO in Phase Compensation mode, connect tx_clkout (402.83 MHz) to
tx_coreclkin and connect rx_clkout (402.83 MHz) to rx_coreclkin. If you use
any other source for tx_coreclkin or rx_coreclkin, make sure tx_coreclkin
and rx_coreclkin have 0 PPM difference with the tx_clkout and rx_clkout,
respectively. This example assumes that TX and RX Double Width transfer is enabled.
Figure 55. PMA Direct 25 Gbps x 4 (FEC Off)
E-Tile Native PHY IP
TX PMA
25.78125 Gbps
RX PMA
E-Tile FIFO
E-Tile FIFO
EMIB
Native PHY IP Core Interface
tx_clkout
402.83 MHz
TX Data
tx_coreclkin
rx_coreclkin
rx_clkout
402.83 MHz
RX Data
TX Core FIFO
TX Core FIFO
TX Core FIFO
TX Core FIFO
TX Core FIFO
TX Core FIFO
XCVR
Interface
XCVR
Interface
/2
/2
CH3
E-Tile Native PHY IP
TX PMA
25.78125 Gbps
RX PMA
E-Tile FIFO
E-Tile FIFO
EMIB
tx_clkout
402.83 MHz
TX Data
tx_coreclkin
rx_coreclkin
rx_clkout
402.83 MHz
RX Data
XCVR
Interface
XCVR
Interface
/2
/2
CH2
E-Tile Native PHY IP
TX PMA
25.78125 Gbps
RX PMA
E-Tile FIFO
E-Tile FIFO
EMIB
tx_clkout
402.83 MHz
TX Data
tx_coreclkin
rx_coreclkin
rx_clkout
402.83 MHz
RX Data
XCVR
Interface
XCVR
Interface
/2
/2
CH0
Legend:
TX PMA generated parallel clock (line rate / PMA interface width)
TX PMA generated parallel clock div by 2
RX PMA generated parallel clock div by 2
RX PMA generated parallel clock (line rate / PMA interface width)
4. Clock Network
UG-20056 | 2019.02.04
Intel
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Stratix
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10 E-Tile Transceiver PHY User Guide
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Intel Stratix 10 Specifications

General

Brand	Intel
Model	Stratix 10
Category	Control Unit
Language	English