master and slave channels. The E-Tile transceivers can be used in PLL mode to supply
a clock in this configuration as shown below. Only transceivers in PLL mode can also
be used for clocking all four 25G channels. Using external EMIB clocking also helps
provide a clock to low datarate channels when different datarate channels are placed
in same FEC block, for example, 25GE and 24G CPRI. The following figure shows one
master 25 Gbps channel providing the datapath clock to other three slave 25 Gbps
channels.
Figure 54. PMA Direct 25 Gbps x 4 (FEC On) Independent Configuration
Native PHY IP Core Interface
Legend:
TX PMA generated parallel clock (line rate / PMA interface width)
TX PMA generated parallel clock div by 2
RX PMA generated parallel clock div by 2
RX PMA generated parallel clock (line rate / PMA interface width)
E-Tile Native PHY IP
TX PMA
RX PMA FEC
FEC
E-Tile FIFO
E-Tile FIFO
tx_coreclkin2 805.66 MHz
tx_coreclkin 402.83 MHz
rx_clkout 402.83 MHz
tx_clkout 402.83 MHz
rx_coreclkin
XCVR
IF
XCVR
IF
/2
/2
25.78125 Gbps
Native PHY
(PLL Mode)
TX Core
FIFO
RX Core
FIFO
E-Tile Native PHY IP
TX PMA
RX PMA FEC
FEC
E-Tile FIFO
E-Tile FIFO
tx_coreclkin2 805.66 MHz
tx_coreclkin 402.83 MHz
rx_clkout 402.83 MHz
tx_clkout 402.83 MHz
rx_coreclkin
XCVR
IF
XCVR
IF
/2
/2
25.78125 Gbps
Native PHY
(PLL Mode)
TX Core
FIFO
RX Core
FIFO
E-Tile Native PHY IP
TX PMA
RX PMA FEC
FEC
E-Tile FIFO
E-Tile FIFO
tx_coreclkin2 805.66 MHz
tx_coreclkin 402.83 MHz
rx_clkout 402.83 MHz
tx_clkout 402.83 MHz
rx_coreclkin
XCVR
IF
XCVR
IF
/2
/2
25.78125 Gbps
Native PHY
(PLL Mode)
TX Core
FIFO
RX Core
FIFO
E-Tile Native PHY IP
TX PMA
RX PMA FEC
FEC
E-Tile FIFO
E-Tile FIFO
tx_coreclkin2 805.66 MHz
tx_coreclkin 402.83 MHz
rx_clkout 402.83 MHz
tx_clkout 402.83 MHz
rx_coreclkin
XCVR
IF
XCVR
IF
/2
/2
25.78125 Gbps
Native PHY
(PLL Mode)
TX Core
FIFO
RX Core
FIFO
/2
CH3
Slave
CH2
Slave
CH0
Master
CH1
Slave
4. Clock Network
UG-20056 | 2019.02.04
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10 E-Tile Transceiver PHY User Guide
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