Intel Stratix 10 User Manual

4.2.1. Single 25 Gbps PMA Direct Channel (with FEC) Within a Single FEC
Block
Table 40. Single 25 Gbps PMA Direct Channel (with FEC) Within a Single FEC Block
Configuration
Data Rate TX and RX Double Width PMA Interface Core Interface
25.78125 Gbps Enabled 32 bits 64 bits
For FIFO in Phase Compensation mode, connect half rate tx_clkout (402.83 MHz,
that is, 25.78125 Gbps/64) to tx_coreclkin and rx_coreclkin. If you use any
other source for tx_coreclkin, make sure tx_coreclkin has 0 PPM difference
with tx_clkout.
Figure 51. PMA Direct with FEC
E-Tile Native PHY IP
TX PMA
25.78125Gbps
RX PMA FEC
FEC
E-Tile FIFO
EMIB
Native PHY IP Core Interface
tx_clkout
402.83 MHz
TX Data
tx_coreclkin
rx_coreclkin
rx_clkout
402.83 MHz
RX Data
TX Core
FIFO
XCVR
Interface
XCVR
Interface
/2
/2
/2
E-Tile FIFO
RX Core
FIFO
Legend:
TX PMA generated parallel clock (line rate / PMA interface width)
TX PMA generated parallel clock div by 2
RX PMA generated parallel clock div by 2
RX PMA generated parallel clock (line rate / PMA interface width)
4.2.2. Single 10 Gbps PMA Direct Channel (without FEC)
Table 41. Single 10 Gbps PMA Direct Channel Configuration
Data Rate TX and RX Double Width PMA Interface Core Interface
10.3125 Gbps Enabled 20 bits 40 bits
For FIFO in Phase Compensation mode, connect half rate tx_clkout (257.8125 MHz)
to tx_coreclkin and connect rx_clkout (257.8125 MHz) to rx_coreclkin. If
you use any other source for tx_coreclkin/rx_coreclkin, make sure
tx_coreclkin and rx_coreclkin have 0 PPM difference with tx_clkout and
rx_clkout, respectively
4. Clock Network
UG-20056 | 2019.02.04
Intel
®
Stratix
®
10 E-Tile Transceiver PHY User Guide
Send Feedback
90

Intel Stratix 10 Specifications

General

Brand	Intel
Model	Stratix 10
Category	Control Unit
Language	English