Intel Stratix 10 User Manual

The reset values in this table represents register values after a reset has completed.
Bit Name Description SW Access
HW Access
Protection
Reset
1:0 frac Main operation mode:
0 none: Non-fractured, supporting e.g. 100GE, 128GFC:
One client using all 4 physical lanes.
Register tables indexed by physical lane# only uses entry 0, unless otherwise specified.
1 reserved1
2 reserved2
3 frac4: Fractured, supporting e.g. 25GE, 32GFC:
Four clients, each using 1 physical lane.
RW
RO
-
0x0
9.5.6. rsfec_lane_cfg
Register Name Description Address Addressing Mode
rsfec_lane_cfg_0 RS-FEC per lane configuration 0x40 32-bits
rsfec_lane_cfg_1 0x44
rsfec_lane_cfg_2 0x48
rsfec_lane_cfg_3 0x4C
The reset values in this table represents register values after a reset has completed.
Bit
Name Description SW Access
HW Access
Protection
Reset
3 rs544 Selects the RS encoder/decoder mode:
0: Use RS(528,514).
1: Use RS(544,514).
RW
RO
-
0x0
2 indic_byp Bypass error indication (to reduce latency):
0: Sync headers in the 66b words extracted from uncorrectable FEC codewords are
deliberately invalidated.
1: 66b words extracted from uncorrectable codewords are not explicitly marked bad.
When number of symbol errors in a block of 8192 consecutive codewords has
exceeded 417 with RS528 and 6380 with RS544, then sync header errors will be
generated towards the PCS layer for a period of 60ms to 75ms.
RW
RO
-
0x0
1 scr Set to enable PN-5280 scrambling/descrambling.
Must be set to 1 when RS-FEC_CORE_CFG.frac = frac4 and RS-FEC_LANE_CFG.fc = 1
(i.e. 32GFC), otherwise it must be set to 0.
RW
RO
-
0x0
0 fc Set to enable Fibre Channel mode. RW
RO
-
0x0
9.5.7. tx_aib_dsk_status
Description
Address Addressing Mode
Status fields for TX Deskew 0x104 32-bits
9. Register Map
UG-20056 | 2019.02.04
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10 E-Tile Transceiver PHY User Guide
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Intel Stratix 10 Specifications

General

Brand	Intel
Model	Stratix 10
Category	Control Unit
Language	English