Intel Stratix 10 User Manual

Name Address Bit Offset Type Description
Control [2:0]
read-
write
Select PMA configuration
PMA
Configurat
ion
Loading
Status
0x40144 [0]
read-
only
rcp_load_finish
[1]
read-
only
rcp_load_timeout
[2]
read-
only
rcp_load_busy
Refer to PMA Attribute Codes for details about the PMA attribute codes and values.
Refer to Multiple Reconfiguration Profiles for more information about using the
embedded streamer.
Related Information
• PMA Attribute Codes on page 170
• Multiple Reconfiguration Profiles on page 123
9.1.3. PMA AVMM Registers
Table 61. PMA AVMM Registers
Address Bit Offset Description
0x4
[0] TX datapath clock enable
[1] Transmit full clock out (PMA Clock) enable
[4:2] Transmit data-input select
[5]
Transmit full clock out (clk_tx_adapt) select
[6] Transmit clock datapath select
[7] Transmit adaptation order select. Determines how 64 bits are sent to 32-bit transceiver
channel
0x5
[1:0] Transmit multi-lane data select
[2] TX Gearbox clock enable
[3] TX datapath clock enable
[4] TX PCS div2 clock input enable
[5] TX FEC div2 clock input enable
[6] TX EHIP div2 clock input enable
[7] TX direct clock input enable
0x6
[0] RX datapath clock enable
[1]
Receive full clock out (rx_pma_clk) enable
[2]
Receive half clock out (rx_pcs_clk) enable
[3]
Receive div66 clock out (rx_pcs_div66_clk) enable
continued...
9. Register Map
UG-20056 | 2019.02.04
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10 E-Tile Transceiver PHY User Guide
167

Intel Stratix 10 Specifications

General

Brand	Intel
Model	Stratix 10
Category	Control Unit
Language	English