Intel Stratix 10 User Manual

7.16.2. Alternative Method for Setting PMA Attributes
In addition to loading PMA attributes one by one, you can use registers 0x200 to
0x203 to load a set of common PMA attributes to all transceiver channels in the
instance. Please refer to Reading and Writing PMA Analog Parameters Using Attributes
for more details. Refer to Configuring a PMA Parameter Using Native PHY IP for an
example.
Related Information
• Configuring a PMA Parameter Using Native PHY IP on page 157
• Reading and Writing PMA Analog Parameters Using Attributes on page 182
7.17. Dynamic Reconfiguration Revision History
Document
Version
Changes
2019.02.04 Made the following changes:
• Added Loading IP Configuration Settings.
• Added Loading IP Configuration Settings Process.
• Added Alternative Method for Setting PMA Attributes.
2018.10.08 Made the following changes:
• Changed some descriptions in the "Dynamic Reconfiguration" section.
• Added a feature to the "Intel Stratix 10 Dynamic Reconfiguration Feature Support" table.
• Updated the reconfig_write waveform in the "Writing to the Reconfiguration Interface" figure.
• Switched the order of Disable PMA internal or serial loopback and Enable Initial RX Equalizer steps
in the "Dynamic Reconfiguration with Native PHY in Automatic Reset Mode" figure.
• Changed Step 4 in the "Embedded Reconfiguration Streamer" section.
• Added step 8f and 9 to Switching Reference Clocks.
• Added a reference to PMA Analog Reset from Switching Reference Clocks.
2018.07.18 Made the following changes:
• Added reconfiguring the PMA between NRZ and PAM4 (non high datarate) modes as a feature to the
"Dynamic Reconfiguration Feature Support" table.
• Added Multiple Reconfiguration Profiles.
• Updated Reconfiguration Files with entirely new information.
• Added Embedded Reconfiguration Streamer.
• Updated the steps in the Switching Reference Clocks section.
2018.05.15 Made the following changes:
• Removed "Configuration Files," "Multiple Dynamic Reconfiguration Profiles," "Changing Analog PMA
Settings," "Multiple Dynamic Reconfiguration Profiles," "Embedded Dynamic Reconfiguration
Streamer," "PMA Attribute Sequencer," and "Native PHY IP Core or Clocking Resources Guided
Reconfiguration Flow" sections.
• Added RX adaptation to the list of PMA analog features.
• Removed reconfig_rsfec pending support.
• Removed "PCS" from all sections.
• Updated MIF file format in the "Configuration Files" section.
• Updated the configuration file location in the "Multiple Reconfiguration Profiles" section.
• Removed the "Register read/write sequencer" block from the "Arbitration" figure and list of
programmable registers.
• Deleted data-rate-non-specific recommendation from the "Recommendations for Dynamic
Reconfiguration" section.
• Replaced the text in the "Steps to Perform Dynamic Reconfiguration" section with "Dynamic
Reconfiguration with Reset Controller in Automatic Mode" and "Dynamic Reconfiguration with Reset
Controller in Manual Mode (required for fractured RS-FEC mode)."
• Changed "Direct Reconfiguration Flow" with "PMA Register Read/Write Details."
continued...
7. Dynamic Reconfiguration
UG-20056 | 2019.02.04
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10 E-Tile Transceiver PHY User Guide
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Intel Stratix 10 Specifications

General

Brand	Intel
Model	Stratix 10
Category	Control Unit
Language	English