Intel Stratix 10 User Manual

The reset values in this table represents register values after a reset has completed.
Bit Name Description SW Access
HW Access
Protection
Reset
11:8 tx_dsk_active_chans Active Channels.
1 bit per channel (bit0 = AIB chan 0). Indicates which AIB channels
received a deskew marker (since reset). This is a sticky bit that clears
on reset and i_dsk_clear. For logging in RS-FEC CSR. CSR may treat
this as a real time status signal.
RO
WO
-
0x0
7:4 tx_dsk_monitor_err Skew Monitor Error Detected
1 bit per channel (bit0 =AIB chan 0). This field only updates after a
successful deskew. A non-zero value indicates that the deskewed
Markers are no longer in alignment. 1 in each bit position indicates that
the corresponding channel received a Deskew Marker before ALL
enabled-channels received them.
Note: You can see which channels received Deskew Markers (at all) via
o_tx_dsk_active_chans.
RO
WO
-
0x0
3:1 tx_dsk_status Total-Channel-to-channel-skew status
Valid when tx_dsk_eval_done=1. Reports the total skew detected at the
end of the deskew procedure
0..5: 0..5 cycles of delay added to remove skew
6..7:error detected
RO
WO
-
0x0
0 tx_dsk_eval_done Deskew Complete
Means Deskew procedure has completed
RO
WO
-
0x0
9.5.8. rsfec_debug_cfg
Description
Address Addressing Mode
Extra config/debug on fec_clock 0x108 32-bits
The reset values in this table represents register values after a reset has completed.
Bit
Name Description SW Access
HW Access
Protection
Reset
31 main_rst Main Soft Reset
Setting this bit causes main soft reset of rsfec including tx/rx path
RW
RO
-
0x0
29 rx_rst RX Soft Reset
Setting this bit causes soft reset of the RX datapath in RS-FEC Core
RW
RO
-
0x0
28 tx_rst TX Soft Reset
Setting this bit causes soft reset of the TX datapath in RS-FEC Core
RW
RO
-
0x0
7:4 shadow_clear Clear Rsfec Counters
1: Clear the collection and shadow counters so that the next shadow request or
snapshot will start from 0.
If the counters are not cleared, they will continue counting and rollover.
RW
RO
-
0x0
3:0 shadow_req RW
RO
-
0x0
9. Register Map
UG-20056 | 2019.02.04
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10 E-Tile Transceiver PHY User Guide
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Intel Stratix 10 Specifications

General

Brand	Intel
Model	Stratix 10
Category	Control Unit
Language	English