Intel Stratix 10 User Manual

Bit Name Description SW Access
HW Access
Protection
Reset
2'b11 : Debug Mode - Select Loopback from EHIP TX Data.
5:4 core_rx_out_sel1 RS-FEC RX Output Select For Lane 1
Indicates which data to select for rsfec core TX input. All lanes should
have same selection for EHIP and RS-FEC_DIRECT_100G modes. Does
not work for TX Select of Elane and Loopback
2'b00 : Bypass RS-FEC RX paths - data from XCVRIF fec / pcs path
(normal bypass)
2'b01 : Select output of RS-FEC RX.
2'b10 : Bypass RS-FEC RX paths - data from XCVRIF fec path for both
ehip and elane
2'b11 : Debug Mode - Select Loopback from EHIP TX Data.
RW
RO
-
0x0
1:0 core_rx_out_sel0 RS-FEC RX Output Select For Lane 0
Indicates which data to select for rsfec core TX input. All lanes should
have same selection for EHIP and RS-FEC_DIRECT_100G modes. Does
not work for TX Select of Elane and Loopback
2'b00 : Bypass RS-FEC RX paths - data from XCVRIF fec / pcs path
(normal bypass)
2'b01 : Select output of RS-FEC RX.
2'b10 : Bypass RS-FEC RX paths - data from XCVRIF fec path for both
ehip and elane
2'b11 : Debug Mode - Select Loopback from EHIP TX Data.
RW
RO
-
0x0
9.5.4. tx_aib_dsk_conf
Description
Address Addressing Mode
Defines the configuration fields for TX Deskew 0x20 32-bits
The reset values in this table represents register values after a reset has completed.
Bit
Name Description SW Access
HW Access
Protection
Reset
7 tx_deskew_clear AIB Deskew clear
0:Normal deskew operation
1:TX AIB deskew circuit in reset
RW
RO
-
0x0
3:0 tx_deskew_chan_sel Specifies which channels to include in the deskew procedure
1= include
RW
RO
-
0x0
9.5.5. rsfec_core_cfg
Description
Address Addressing Mode
RS-FEC core configuration 0x30 32-bits
9. Register Map
UG-20056 | 2019.02.04
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Intel Stratix 10 Specifications

General

Brand	Intel
Model	Stratix 10
Category	Control Unit
Language	English