Intel Stratix 10 User Manual

Bit Name Description SW Access
HW Access
Protection
Reset
Setting these bits enables the clock/lane for RS-FEC mode. This also enables
the RX path to the RS-FEC core for that lane (else 0 the valid/data). One bit
per lane [bit0=lane0]. If all lanes are disabled, the fec_clk will be turned off.
One of these bits MUST be set in order to properly access the registers which
are in the fec_clk domain (rsfec_cfgcsr_core_csr).
2:0 rsfec_clk_sel Clock selection for RS-FEC
Indicates which clock to use for rsfec core clock. In addition one of the
fec_lane_ena bits must be set for the clock to propagate.
3'b000 : Select Ehip clock
3'b100 : Select AIB Adapter TX clock 0
3'b101 : Select AIB Adapter TX clock 1
3'b110 : Select AIB Adapter TX clock 2
3'b111 : Select AIB Adapter TX clock 3
All other inputs are invalid and defaults to Ehip clock
RW
RO
-
0x0
9.5.2. rsfec_top_tx_cfg
Description Address Addressing Mode
RS-FEC TX configuration register 0x10 32-bits
The reset values in this table represents register values after a reset has completed.
Bit
Name Description SW Access
HW Access
Protection
Reset
31:28 core_tx_pcs_bypass FEC TX Bypass
Setting this bit enables elane tx bypass to XCVRIF. This is one bit per
lane [bit0=lane0]
RW
RO
-
0x0
14:12 core_tx_in_sel3 RS-FEC TX Select For Lane 3
Indicates which data to select for rsfec core TX input
3'b000 : Select EHIP Core TX Data - all lanes should have same
selection
3'b001 : Select EHIP Lane TX Data
3'b010 : Select AIB Lane TX Data with Deskew - should be same for all
lanes
3'b011 : Select AIB Lane TX Data No Deskew
3'b110 : FEC Lane Disabled - tie inputs to 0
3'b111 : Debug Mode - Select Loopback from output of RS-FEC RX
RW
RO
-
0x0
10:8 core_tx_in_sel2 RS-FEC TX Select For Lane 2
Indicates which data to select for rsfec core TX input
3'b000 : Select EHIP Core TX Data - all lanes should have same
selection
3'b001 : Select EHIP Lane TX Data
3'b010 : Select AIB Lane TX Data with Deskew - should be same for all
lanes
3'b011 : Select AIB Lane TX Data No Deskew
3'b110 : FEC Lane Disabled - tie inputs to 0
3'b111 : Debug Mode - Select Loopback from output of RS-FEC RX
RW
RO
-
0x0
6:4 core_tx_in_sel1 RS-FEC TX Select For Lane 1
Indicates which data to select for rsfec core TX input
RW
RO
-
0x0
continued...
9. Register Map
UG-20056 | 2019.02.04
Intel
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Stratix
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10 E-Tile Transceiver PHY User Guide
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Intel Stratix 10 Specifications

General

Brand	Intel
Model	Stratix 10
Category	Control Unit
Language	English