Intel Stratix 10 User Manual

9.5.31. rsfec_corr_0s_cnt (High)
Register Name Description Address Addressing Mode
rsfec_corr_0s_cnt_0_hi RS-FEC number of bits corrected 0->1 for the
lane (high word: bits 63 to 32)
0x264 32-bits
rsfec_corr_0s_cnt_1_hi 0x26C
rsfec_corr_0s_cnt_2_hi 0x274
rsfec_corr_0s_cnt_3_hi 0x27C
The reset values in this table represents register values after a reset has completed.
Bit Name Description SW Access
HW Access
Protection
Reset
31:0 stat Statistics value. RO
WO
-
0x0000 0000
9.5.32. rsfec_corr_1s_cnt (Low)
Register Name Description Address Addressing Mode
rsfec_corr_1s_cnt_0_lo RS-FEC number of bits corrected 1->0 for the lane
(low word: bits 31 to 0)
0x280 32-bits
rsfec_corr_1s_cnt_1_lo 0x288
rsfec_corr_1s_cnt_2_lo 0x290
rsfec_corr_1s_cnt_3_lo 0x298
The reset values in this table represents register values after a reset has completed.
Bit
Name Description SW Access
HW Access
Protection
Reset
31:0 stat Statistics value. RO
WO
-
0x0000 0000
9.5.33. rsfec_corr_1s_cnt (High)
Register Name
Description Address Addressing Mode
rsfec_corr_1s_cnt_0_hi RS-FEC number of bits corrected 1->0 for the lane
(high word: bits 63 to 32)
0x284 32-bits
rsfec_corr_1s_cnt_1_hi 0x288
rsfec_corr_1s_cnt_2_hi 0x294
rsfec_corr_1s_cnt_3_hi 0x29C
The reset values in this table represents register values after a reset has completed.
Bit
Name Description SW Access
HW Access
Protection
Reset
31:0 stat Statistics value. RO 0x0000 0000
9. Register Map
UG-20056 | 2019.02.04
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Intel Stratix 10 Specifications

General

Brand	Intel
Model	Stratix 10
Category	Control Unit
Language	English