Intel Stratix 10 User Manual

Design modularity – Local changes to the number of transceiver reset signals at a
lower hierarchy in a module does not require a chain of interface changes up to the
Master TRS hierarchy, especially if the transceiver instance is deep down in the design
hierarchy.
Tradeoffs
It is harder to debug a possible connectivity issue in Synthesis than debugging the
RTL.
Any issue with the instantiation and connectivity needs to be fixed in Synthesis instead
of in the design.
6.7. Block Diagrams
Figure 75. General Block Diagram for Reset Controller when Use Separate TX/RX Reset
Per Channel is Turned ON and Enable Individual TX and RX Reset is Turned
OFF
E-Tile Native PHY IP
Reset Controller [N]
Reset Controller [0]
rx_ready[0]
tx_ready[0]
reset[0]
rx_ready[N]
tx_ready[N]
reset[N]
6. Resetting Transceiver Channels
UG-20056 | 2019.02.04
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10 E-Tile Transceiver PHY User Guide
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Intel Stratix 10 Specifications

General

Brand	Intel
Model	Stratix 10
Category	Control Unit
Language	English