Intel Stratix 10 User Manual

AVMM masters interact with the reconfiguration interface by performing AVMM read
and write operations to initiate a dynamic reconfiguration of specific transceiver
parameters. The dynamic reconfiguration interfaces are compliant with AVMM
specifications.
Figure 79. Reconfiguration Interface Ports with Shared Native PHY Reconfiguration
Interface
Native PHY IP Core
reconfig_clk
reconfig_reset
reconfig_write
reconfig_read
reconfig_writedata
reconfig_address
reconfig_readdata
reconfig_waitrequest
7.3. Unsupported Features
Dynamic reconfiguration between the following modes is not supported by the
Transceiver Native PHY IP core:
• PMA direct high data rate PAM4
• PMA-direct bonded mode
• Non RS-FEC to RS-FEC reconfiguration
7.4. Reading from the Dynamic Reconfiguration Interface
Reading from the reconfiguration interface of the Transceiver Native PHY IP core
retrieves the current value at a specific address.
7. Dynamic Reconfiguration
UG-20056 | 2019.02.04
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10 E-Tile Transceiver PHY User Guide
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Intel Stratix 10 Specifications

General

Brand	Intel
Model	Stratix 10
Category	Control Unit
Language	English