Intel Stratix 10 User Manual

1.2.2. Stratix 10 MX H-Tile and E-Tile Configurations
Intel Stratix 10 MX devices combine the programmability and flexibility of Intel Stratix
10 FPGAs and SoCs with 3D stacked high-bandwidth memory 2 (HBM2). The dynamic
random access memory (DRAM) tile is physically connected to the FPGA using Intel's
Embedded Multi-die Interconnect Bridge (EMIB) technology.
Figure 5. Intel Stratix 10 MX Device with 3 E-Tiles, 1 H-Tile (96 Transceiver Channels)
and 2 HBM2
E-Tile
(24 Channels)
HSSI_2_0
Package Substrate
EMIBEMIB
Core Fabric
®
MX 1650 UF55 (F2912)
HBM2
E-Tile
(24 Channels)
HSSI_2_1
EMIBEMIB
HBM2
MX 2100 UF55 (F2912)
E-Tile
(24 Channels)
HSSI_0_1
H-Tile
(24 Channels)
HSSI_0_0
4 GByte
4 GByte
There is no package migration between Intel Stratix 10 MX and Intel Stratix 10 TX
device families (H-Tile and E-Tile) or Intel Stratix 10 GX/SX device families.
1.3. Transceiver Counts in Stratix 10 TX/MX Devices
Table 3. Transceiver Counts in Intel Stratix 10 TX Devices with E-Tiles (NF43, SF50,
UF50, YF55)
The number in the Intel Stratix 10 TX Device Name column indicates the device's Logic Element (LE) count (in
thousands LEs).
Intel Stratix 10 TX Device Name
F1760
NF43
(42.5 mm x 42.5 mm)
Transceivers (E, H)
F2397
SF50, UF50
(50 mm x 50 mm)
Transceivers (E, H)
F2912
YF55
(55 mm x 55 mm)
Transceivers (E, H)
TX 400 24, 24 N/A N/A
TX 650 24, 24 N/A N/A
TX 850 24, 24 48, 24 N/A
TX 1100 24, 24 48, 24 N/A
TX 1650 N/A 72, 24 N/A
TX 2100 N/A 72, 24 N/A
TX 2500 N/A 72, 24 120, 24
TX 2800 N/A 72, 24 120, 24
1. Intel
®
Stratix
®
10 E-Tile Transceiver PHY Overview
UG-20056 | 2019.02.04
Intel
®
Stratix
®
10 E-Tile Transceiver PHY User Guide
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Intel Stratix 10 Specifications

General

Brand	Intel
Model	Stratix 10
Category	Control Unit
Language	English