Intel Stratix 10 User Manual

Channel bonding is a common technique used to minimize high speed serial lane-lane
transmit skew for multi-lane protocols. Channel bonding is supported under the
following conditions:
•
Using refclk[0]
• NRZ PMA direct mode
• Data rate limited to:
— 16-bit (parallel data width): 12.0 Gbps
— 20-bit (parallel data width): 16.0 Gbps
— 32-bit (parallel data width): 28.0 Gbps
Note: Bonding is only supported within a tile. Bonding is not supported within a package
across different tiles, even if the reference clock is shared.
Figure 12. TX and RX with the Same Reference Clock
This configuration shows refclk[1] being used for TX and RX on both channels, enabling use of the same
reference clock.
Transmitter
Receiver
Channel 0
Unused
Transmitter
Receiver
Channel 1
refclk[0] refclk[1]
refclk_in_B
refclk[8:2]
refclk_in_B
Related Information
• Intel Stratix 10 Device Datasheet
• Intel Stratix 10 Device Family Pin Connection Guidelines
1.4.4. Ethernet Hard IP (EHIP)
The Ethernet Hard IP is a hardened core of assorted multi-lane and single-lane
Ethernet components.
Intel Stratix 10 E-Tiles include four instances of the Ethernet Hard IP, which in turn
supports up to four multi-lane Ethernet MAC stacks, or 24 channels of single-lane
Ethernet channel (MAC/PCS) support.
1. Intel
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10 E-Tile Transceiver PHY Overview
UG-20056 | 2019.02.04
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Intel
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10 E-Tile Transceiver PHY User Guide
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Intel Stratix 10 Specifications

General

Brand	Intel
Model	Stratix 10
Category	Control Unit
Language	English