Each Hard IP instance contains a full-featured multi-lane Ethernet (EHIP_CORE) Media
Access Control (MAC) layer, which offers a number of interfacing options from the
FPGA fabric. The multi-lane core can be used for 100G Ethernet applications. In
addition to the multi-lane MAC stack, the Ethernet Hard IP contains six instances of a
single-lane Ethernet channel.
Figure 13. Ethernet Hard IP Overview
Reed Solomon Forward Error Correction (RS-FEC) is configurable for single-lane 10 GbE or 25 GbE interfaces as
well as multi-lane 100 GbE.
Channels: 0, 1, 2, 3, 4, 5
Protocol: 25GbE
EHIP_LANE
RS-FEC: Yes (528, 514) - Fractured
Channels: 6, 7
Protocol: 10GbE
EHIP_LANE
RS-FEC: No
Channels: 8, 9, 10, 11
Protocol: 100GbE (NRZ)
EHIP_CORE
RS-FEC: Yes (528, 514) - Aggregate
Channels: 12, 13, 14, 15
Protocol: 100GbE (NRZ) + PTP
EHIP_CORE + PTP
RS-FEC: Yes (528, 514) - Aggregate
Channels: 16, 17
Protocol: Used for PTP
EHIP_CORE
RS-FEC: No
Channels: 18, 19
Protocol: Unused
N/A
RS-FEC: N/A
Channels: 20, 21, 22, 23
Protocol: 100GbE (PAM4)
EHIP_CORE
RS-FEC: Yes (544, 514) - Aggregate
The Intel Stratix 10 E-Tile implementation of the Ethernet Hard IP provides the
following features and support:
• 4x hardened MACs per Intel Stratix 10 E-Tile
• Each MAC block can be configured as:
— One 100 GbE interface
— Six 10 GbE / 25 GbE interfaces
— Bypassable
• Supports IEEE 1588-2002 standard/Precision Time Protocol (PTP)
— When used with the multi-lane 100 GbE core or 1-4 lanes of the 10 GbE or 25
GbE stack, two additional transceiver channels are configured for 1588. The
location of these two additional channels is hardened for 1588 configuration.
Use the E-Tile Channel Placement Tool to see how the channels are configured
to support 1588.
Related Information
E-Tile Channel Placement Tool
1. Intel
®
Stratix
®
10 E-Tile Transceiver PHY Overview
UG-20056 | 2019.02.04
Intel
®
Stratix
®
10 E-Tile Transceiver PHY User Guide
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