Intel Stratix 10 User Manual

Bit Name Description SW Access
HW Access
Protection
Reset
Only applicable when RSFEC_CORE_CFG.frac = none (100GE/128GFC).
0 not_align RX lanes not aligned (state).
Incoming signal fail, RX lanes not all locked, alignment markers not unique or skew
too large.
Only applicable when RSFEC_CORE_CFG.frac = none (100GE/128GFC).
W1C
W1S
-
0x0
9.5.17. rsfec_lanes_rx_inten
Description Address Addressing Mode
RS-FEC combined lanes RX interrupt enable - set to 1 to enable
rsfec_lanes rx lane interrupt
0x18C 32-bits
The reset values in this table represents register values after a reset has completed.
Bit Name Description SW Access
HW Access
Protection
Reset
1 not_deskew All RX lanes locked but the alignment markers were not unique or the skew was too
large.
This is an event signal, so use .not_align above instead to determine the alignment
state.
Restarts the synchronization.
Only applicable when RSFEC_CORE_CFG.frac = none (100GE/128GFC).
RW
RO
-
0x0
0 not_align RX lanes not aligned (state).
Incoming signal fail, RX lanes not all locked, alignment markers not unique or skew
too large.
Only applicable when RSFEC_CORE_CFG.frac = none (100GE/128GFC).
RW
RO
-
0x0
9.5.18. rsfec_ln_mapping_rx
Register Name
Description Address Addressing Mode
rsfec_ln_mapping_rx
_0
RS-FEC FEC lane mapping 0x1A0 32-bits
rsfec_ln_mapping_rx
_1
0x1A4
rsfec_ln_mapping_rx
_2
0x1AB
rsfec_ln_mapping_rx
_3
0x1AC
The reset values in this table represents register values after a reset has completed.
Bit
Name Description SW Access
HW Access
Protection
Reset
1:0 fec_lane FEC lane# received on each physical lane.
Only applicable when RSFEC_CORE_CFG.frac = none (100GE/128GFC).
RO
WO
-
0x0
9. Register Map
UG-20056 | 2019.02.04
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Intel Stratix 10 Specifications

General

Brand	Intel
Model	Stratix 10
Category	Control Unit
Language	English