Intel Stratix 10 User Manual

1.4.5. Supported Applications/Modes
Table 6. Supported Applications/Modes
Supported
Application/Mode
EHIP_CORE EHIP_LANE PMA Direct RS-FEC Dual Mode
(1)
PAM4/NRZ
100GbE (4 x 25G) –
NRZ w/ FEC
Yes No No Yes (Aggregate) No NRZ
100GbE (2 x 50G) –
PAM4 w/ FEC
Yes No No Yes (Aggregate) Yes PAM4
100GbE (4 x 25G) –
NRZ w/o FEC
yes No No No No NRZ
32G Fibre Channel w/
FEC
No No Yes Yes (Fractured) No NRZ
25GbE - NRZ w/FEC No Yes No Yes (Fractured) No NRZ
25GbE - NRZ w/o FEC No Yes No No No NRZ
CPRI 24G - NRZ w/
FEC
No Yes No Yes (Fractured) No NRZ
10GbE – NRZ No Yes No No No NRZ
NRZ - 1G to 30G No No Yes No No NRZ
PAM4 - 2G to 30G No No Yes No No PAM4
PAM4 - 30G to 57.8G No No Yes No Yes PAM4
NRZ - 1G to 30G w/
FEC
No No Yes Yes (Fractured) No NRZ
1.4.6. Feature Comparison Between Transceiver Tiles
Table 7. Transceiver Tile Feature Comparison
Feature L-Tile/H-Tile E-Tile
Native PHY IP Configure NRZ mode Configure NRZ and PAM4
PLL IP ATXPLL, fPLL and CMU PLL IPs (available in the
IP catalog)
Embedded in Native PHY and Ethernet Hard
IPs
Reset controller IP Reset controller IP (available in the IP catalog) Embedded in the Native PHY and Ethernet
Hard IP cores
Clocking modes • TX PMA bonding up to 24 channels
• ATXPLL-fPLL and fPLL-fPLL cascade
• VCXO replacement (ATXPLL and fPLL
fractional division support)
Only TX PMA bonding supported
Calibration Power-up calibration and recalibration Power-up calibration and recalibration
Configuration ports For each instantiated IP (Native PHY IP core,
ATXPLL/fPLL), there is one configuration port.
For each instantiated Native PHY IP core,
there are two configuration ports: one for the
Native PHY IP core and another for RS-FEC.
continued...
(1)
PMA Direct high data rate mode
1. Intel
®
Stratix
®
10 E-Tile Transceiver PHY Overview
UG-20056 | 2019.02.04
Send Feedback
Intel
®
Stratix
®
10 E-Tile Transceiver PHY User Guide
21

Intel Stratix 10 Specifications

General

Brand	Intel
Model	Stratix 10
Category	Control Unit
Language	English