Intel Stratix 10 User Manual

Port Name Direction Width Description
Asserts a few clock cycles after deassertion of RX resets.
tx_pma_ready
Output Number of
channels
One per channel. Indicates transceiver channel Transmit calibration
completed.
rx_pma_ready
Output Number of
channels
One per channel. Indicates transceiver channel CDR calibration
completed.
6.9. Resetting Transceiver Channels Revision History
Document
Version
Changes
2019.02.04 Made the following changes:
• Added the "When to Perform a PMA Analog Reset" table.
2018.10.08 Made the following changes:
• Added the RX Reset Duration and Use Separate TX/RX Reset Per Channel parameters to the
"Reset Parameters" table.
• Added the "Reset Controller when Use Separate TX/RX Reset Per Channel is Turned OFF and
Enable Individual TX and RX Reset is Turned OFF" figure.
• Added the "PMA Analog Reset" section.
• Added the "Reset Requirements when RS-FEC is Enabled" table and descriptions about necessary
requirements when RS-FEC is enabled.
•
Changed the description of tx_reset in the "Reset Signals Required for E-Tile" table.
•
Updated the description for rx_transfer_ready and added the rx_pma_ready and
rx_is_lockedtodata signals to the "Native PHY IP Ports With Manual Mode Enabled" table.
• Added a description about RS-FEC behavior in the "Manual Reset Mode" section.
• Added the "Reset Controller Bypass" section and all subsections.
• Added a signal to the "Reset Controller when Use Separate TX/RX Reset Per Channel is Turned
OFF and Enable Individual TX and RX Reset is Turned OFF" figure.
• Added the Enable TX/RX reset sequencing parameter to the "Reset Parameters" table.
2018.07.18 Made the following changes:
• Updated the "RX Reset Deassertion Timing Waveform" sequence.
• Moved AVMM to between first falling edge of rx_reset_req and rx_pma_ready rising edge in "RX
PMA Reconfiguration with Reset Controller in Manual Mode Timing Waveform."
• Moved AVMM to between first falling edge of tx_reset_req and tx_pma_ready rising edge in "TX
PMA Reconfiguration with Reset Controller in Manual Mode Timing Waveform."
2018.05.15 Made the following changes:
• Added the "Enable individual TX and RX reset" Reset Parameter.
• Removed references to the sequencer.
• Moved the "Resetting the Intel Stratix 10 E-Tile Transceiver" task and re-wrote it to encompass both
analog and digital reset procedures.
• Restructured "Automatic Reset Mode."
• Added PMA ready signals to the "Manual Reset Mode" figure.
• Added four Timing Waveforms: RX & TX Reset Assertion and RX & TX PMA Reconfiguration with
Reset Controller in Manual Mode to the "Manual Reset Mode" section.
• Removed PCS Gearbox and RS-FEC Direct from the "Reset Block Architecture" section because the
PCS Gearbox is only for Interlaken and PMA direct with RS-FEC is in fractured mode.
• Added a note to the "TX Reset Sequence in Automatic Mode After Power-Up" figure.
• Added a note to the "RX Reset Sequence in Automatic Mode After Power-Up" figure.
• Removed "PCS" from all sections.
2018.01.31 Initial release.
6. Resetting Transceiver Channels
UG-20056 | 2019.02.04
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10 E-Tile Transceiver PHY User Guide
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Intel Stratix 10 Specifications

General

Brand	Intel
Model	Stratix 10
Category	Control Unit
Language	English