Intel Stratix 10 User Manual

Parameter Value Description
• TX/RX Duplex: Specifies a single channel that supports
both transmission and reception.
The default is TX/RX Duplex.
Number of data channels 1-24 Specifies the number of transceiver channels you want to
implement. The default value is 1. The maximum value is
24.
Enable RSFEC On/Off Enables the RS-FEC functionality.
(2)
Provide separate interface
for each channel
On/Off When selected, the Native PHY IP core presents separate
data, reset, and clock interfaces for each channel rather
than a wide bus.
Enable datapath and
interface reconfiguration
On/Off Enables the ability to preconfigure and dynamically switch
between the RS-FEC enabled and disabled modes.
Number of reference clock
inputs
1-5
(2)
Specifies the desired number of reference clocks intended
for the transmitter AND/OR receiver. This allows for
dynamic clock source switching. Native PHY IP Core allows
up to five clock inputs out of the possible nine for dynamic
clock switching.
Initial TX reference clock
input selection
0 This indicates the starting clock input selection used for
this configuration when dynamically switching between
multiple clock inputs.
Enable dedicated RX
reference clock input
On/Off Option to assign dedicated reference clock for the receiver
instead of sharing it with the transmitter.
Dedicated RX clock input
selection
0-4 When you enable the Enable Receiver dedicated
reference clock input option, you can select the input
clock with this parameter.
2.2.2. PMA Parameters
You can specify values for the following types of PMA parameters:
TX PMA:
• TX PMA Options
• TX PMA Pre-equalization
• TX Clocking Options
RX PMA:
• RX PMA Options
• RX PMA Optional Ports
• RX Clocking Options
(2)
When you enable RS-FEC, the number of data channels is 1-4.
2. Implementing the Transceiver PHY Layer in Intel Stratix 10 Devices
UG-20056 | 2019.02.04
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10 E-Tile Transceiver PHY User Guide
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Intel Stratix 10 Specifications

General

Brand	Intel
Model	Stratix 10
Category	Control Unit
Language	English