Intel Stratix 10 User Manual

7.15. Transceiver Register Map
The transceiver register map provides a list of available PCS, PMA, and EMIB
addresses that are used in the reconfiguration process (the transceiver configuration
file includes details about the registers that are set for a specific transceiver
configuration). Do not use the register map to locate and modify specific registers in
the transceiver. Doing so may result in an illegal configuration. Refer to a valid
transceiver configuration file for legal register values and combinations.
7.16. Loading IP Configuration Settings
You may need to set the PMA RX adaptation settings for optimal transceiver
performance. See the PMA Tuning for more information. There are two methods for
setting the PMA RX adaption values.
• The first method is to use PMA attributes to load the PMA RX adaptation settings
one by one. See PMA Attribute Codes and Configuring a PMA Parameter Tunable
by the Adaptive Engine for details of how to load an adaptation setting.
• The second method is, when you generate the IP, to define up to eight different
PMA configurations in the Native PHY IP to use built-in logic to load one of them to
all transceiver channels in the instance at run-time. SeeLoading IP Configuration
Settings Process for more details and Configuring a PMA Parameter Using Native
PHY IP for an example.
Related Information
• Loading IP Configuration Settings on page 137
• PMA Tuning on page 68
• Loading IP Configuration Settings Process on page 137
• Configuring a PMA Parameter Tunable by the Adaptive Engine on page 155
• PMA Attribute Codes on page 170
7.16.1. Loading IP Configuration Settings Process
1. Use the control and status register 0x40143 to load a profile into the PMA.
Register 0x40143[2:0] selects which configuration to load and 0x40143[7]
indicates to the built-in logic to do the actual load.
2. Poll register 0x40144[0] until it becomes 1 to indicate the configuration loading
has completed.
3. Set register 0x200 to register 0x203 as indicated in Loading Parameters into the
Receiver.
4. Poll register 0x207[7] until it becomes 1 to indicate the IP configuration has been
loaded to all transceiver channels. The bit self-clears.
5. Check register 0x204[0]. A '0' indicates the loading was successful.
Related Information
Loading Parameters into the Receiver on page 183
7. Dynamic Reconfiguration
UG-20056 | 2019.02.04
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10 E-Tile Transceiver PHY User Guide
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Intel Stratix 10 Specifications

General

Brand	Intel
Model	Stratix 10
Category	Control Unit
Language	English