Intel Stratix 10 - Page 18

Figure 11. Single Reference Clock Used Across two E-Tiles
Tile 3
Tile 2
Tile 1
Package
PCB
9
9
9
Clock source 1
Clock source 2
Transmitter
Receiver
Transmitter
Receiver
Transceiver
Transceiver
REFCLK
REFCLK_0 -
REFCLK_8
+
–
Divide
by 2
LVPECL
+
–
Divide
by 2
LVPECL
+
–
Divide
by 2
LVPECL
+
–
Divide
by 2
LVPECL
+
–
Divide
by 2
LVPECL
+
–
Divide
by 2
LVPECL
+
–
Divide
by 2
LVPECL
+
–
Divide
by 2
LVPECL
+
–
Divide
by 2
LVPECL
Transmitter
Receiver
Transmitter
Receiver
Transceiver
Transceiver
REFCLK
+
–
Divide
by 2
LVPECL
+
–
Divide
by 2
LVPECL
+
–
Divide
by 2
LVPECL
+
–
Divide
by 2
LVPECL
+
–
Divide
by 2
LVPECL
+
–
Divide
by 2
LVPECL
+
–
Divide
by 2
LVPECL
+
–
Divide
by 2
LVPECL
+
–
Divide
by 2
LVPECL
Transmitter
Receiver
Transmitter
Receiver
Transceiver
Transceiver
REFCLK
+
–
Divide
by 2
LVPECL
+
–
Divide
by 2
LVPECL
+
–
Divide
by 2
LVPECL
+
–
Divide
by 2
LVPECL
+
–
Divide
by 2
LVPECL
+
–
Divide
by 2
LVPECL
+
–
Divide
by 2
LVPECL
+
–
Divide
by 2
LVPECL
+
–
Divide
by 2
LVPECL
REFCLK_0 -
REFCLK_8
REFCLK_0 -
REFCLK_8
All 24 channels have access to all nine reference clock options. This provides:
• Full flexibility on selecting reference clocks on a per-channel basis
•
Channel bonding enabled using refclk[0]
In full duplex mode, each channel can dynamically select any of the nine reference
clocks. If RX and TX channels require different clock frequencies, refclk[1] must be
used as one of the two clocks.
1. Intel
®
Stratix
®
10 E-Tile Transceiver PHY Overview
UG-20056 | 2019.02.04
Intel
®
Stratix
®
10 E-Tile Transceiver PHY User Guide
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