Address Bit Offset Description
[4] Receiver adaptation order select. Determines how 64 bits are combined from 32-bit
transceiver channel
[6:5] Receiver adapter data select
[7] Receiver reverse bit order in Gearbox
0x7
[0] Receiver reverse 64/66 sync header bit order in Gearbox
[1] RX FIFO Read clock enable
[2] Receive Gearbox and FIFO write clock enable
[4:3]
Receive direct-data mode multi-lane data select. Only active if cfg_rx_adapter_sel
is not equal to b'01. These are one-hot encoded
[6:5] Select RX FIFO Read clock
[7] RX adapter clock enable
0x8
[0] Reverse data bit transmission order in TX Gearbox
[1] Reverse 64/66 sync header bit order transmission in TX Gearbox
[3] Dynamic bitslip enable for TX Gearbox
[5] Specify 64/66 sync header location in TX Gearbox
0x9
[1:0] TX Deskew multi-lane mode select
[3:2] TX deskew bits
00 = not yet received a deskew-bit
01 = not aligned
10 = received 1 set of aligned deskew-bits
11 = received 16 sets of aligned deskew-bits
[4] TX deskew alignment status
0 = not aligned or not enabled or didn't receive a deskew-bit
1 = aligned
[5] RX FIFO bit-67 select
0xA
[2:0] Transmit deskew enable (using one-hot encoding)
[5] Dynamic rx_bitslip enable
0x10
[4:0] Transceiver interface RX FIFO empty threshold
[7:6] Transceiver interface RX FIFO almost empty threshold
0x11
[2:0] Transceiver interface RX FIFO almost empty threshold
[7:4] Transceiver interface RX FIFO full threshold
0x12
[0] Transceiver interface RX FIFO full threshold
[6:2] Transceiver interface RX FIFO almost full threshold
0x13
[6] RX FIFO Read when Empty
[7] RX FIFO Write when Full
0x14
[4:0] Transceiver interface TX FIFO empty threshold
[7:6] Transceiver interface TX FIFO almost empty threshold
0x15
[2:0] Transceiver interface TX FIFO almost empty threshold
[7:4] Transceiver interface TX FIFO full threshold
continued...
9. Register Map
UG-20056 | 2019.02.04
Intel
®
Stratix
®
10 E-Tile Transceiver PHY User Guide
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