Intel Stratix 10 User Manual

Address Bit Offset Description
0x16
[0] Transceiver interface TX FIFO full threshold
[6:2] Transceiver interface TX FIFO almost full threshold
0x17
[5:4] TX FIFO Phase Compensation mode
[6] TX FIFO Write when Full
[7] TX FIFO Read when Empty
0x1C [7:0]
Transmit output value [31:0] when the user_reset is active (after FPGA initialization)
0x1D [7:0]
Transmit output value [31:0] when the user_reset is active (after FPGA initialization)
0x1E [7:0]
Transmit output value [31:0] when the user_reset is active (after FPGA initialization)
0x1F [7:0]
Transmit output value [31:0] when the user_reset is active (after FPGA initialization)
0x20 [7:0]
Transmit output value [63:32] when the user_reset is active (after FPGA initialization)
0x21 [7:0]
Transmit output value [63:32] when the user_reset is active (after FPGA initialization)
0x22 [7:0]
Transmit output value [63:32] when the user_reset is active (after FPGA initialization)
0x23 [7:0]
Transmit output value [63:32] when the user_reset is active (after FPGA initialization)
0x24 [2:0]
Transmit output value [66:64] when the user_reset is active (after FPGA initialization)
0x34
[1:0]
Serialization factor for rx_bit_counter
[7:4]
The value at which rx_bit_counter should reset to 0. Set to 5280-32 for RS-FEC
0x35 [7:0]
The value at which rx_bit_counter should reset to 0. Set to 5280-32 for RS-FEC
0x36
[0]
The value at which rx_bit_counter should reset to 0. Set to 5280-32 for RS-FEC
[3] Read-Write self clear
[4]
transmit div66 clock out (tx_pcs_div66_clk) enable
0x37
[0]
Transmit sclk_enable
[2:1] Increment TX FIFO latency select
[4] Receive sclk_enable
[6:5] Increment RX FIFO latency select
[7] Async latency pulse select
0x38
[0] Duty cycle correction: duty cycle correction bypass disable
[1] DCC: DCC master enable
[2] DCC: select continuous cal
0x3C [1] DCC : enable for FSM
0x80 [7:0] Core PMA attribute control
0x81 [7:0] Core PMA attribute control
0x84 [7:0] PMA attribute data
0x85 [7:0] PMA attribute data
0x86 [7:0] PMA attribute code
0x87 [7:0] PMA attribute code
continued...
9. Register Map
UG-20056 | 2019.02.04
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10 E-Tile Transceiver PHY User Guide
169

Intel Stratix 10 Specifications

General

Brand	Intel
Model	Stratix 10
Category	Control Unit
Language	English