Intel Stratix 10 User Manual

Table 48. Reset Controller Bypass Ports
Port Input/Output Description
rx_aib_reset
Input Resets the RX EMIB datapath
rx_pmaif_reset
Input Resets the RX PMA digital logic
rx_rsfec_reset
Input Resets the RX RS-FEC datapath
rx_transfer_ready
Output Output from the Native PHY IP core indicating the RX EMIB
datapath is ready
rx_pma_ready
Output Output from the PMA indicating the RX PMA is ready
rx_is_lockedtodata
Output Output from the Native PHY indicating RX CDR is locked
rsfec_reset
Input Resets all (TX and RX) RS-FEC logic
tx_aib_reset
Input Resets the TX EMIB datapath
tx_pmaif_reset
Input Resets the TX PMA digital logic
tx_rsfec_reset
Input Resets the TX RS-FEC datapath
tx_transfer_ready
Output Output from the Native PHY IP core indicating the TX EMIB
datapath is ready
tx_PMA_ready
Output Output from the PMA indicating the TX PMA is ready. This must be
asserted before asserting or deasserting any TX resets
Figure 72. Reset Controller Bypass Ports
E-Tile Native PHY IP
Reset Controller
RS-FEC
EMIB
PMA Interface
Master TRS
Request
Acknowledgement
TX
RX
PMA
rsfec_reset
tx_rsfec_reset
rx_rsfec_reset
tx_aib_reset
rx_aib_reset
tx_transfer_ready
rx_transfer_ready
tx_pma_ready
rx_pma_ready
tx_pmaif_reset
rx_pmaif_reset
6.5.3.2. Reset Controller Bypass Reset Procedure
In Reset Controller Bypass mode, the reset controller is bypassed and therefore the
local TRS and master TRS blocks are not implemented to circulate and stagger the
resets.
Because the RS-FEC is enabled, you must complete the TX reset on a specific channel
before resetting the RX on that channel. Ensure the PMA is ready before asserting or
deasserting reset to the individual transceiver digital blocks. Ensure the
6. Resetting Transceiver Channels
UG-20056 | 2019.02.04
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Intel Stratix 10 Specifications

General

Brand	Intel
Model	Stratix 10
Category	Control Unit
Language	English