Intel Stratix 10 User Manual

Note:
The Master TRS automatically deasserts the reset_ack output after 400 µs
if you have not deasserted the reset_req input. In that case, you must
deassert and reassert the reset_req input to enter the round robin pool
again.
6. The Master TRS goes to the next request in a round robin fashion and waits 200
ns before asserting the next reset_ack.
The figure below shows how to use the tx_reset_req/rx_reset_req inputs to
request a reset window and how tx_reset_ack/rx_reset_ack marks the Master
TRS returning a valid reset window.
Figure 65. Manual Mode Reset Timing Model
During the timing window when the reset_ack output is high, reset the blocks in sequence. The numbers
refer to the steps above.
t t t t
reset_req[0]
reset_req[1]
reset_req[2]
reset_req[3]
reset_ack[0]
reset_ack[1]
reset_ack[2]
reset_ack[3]
t = 200 ns
1
2
4
5
6
Figure 66 on page 109 and Figure 67 on page 110 below show how to assert TX and
RX reset.
Figure 66. RX Reset Assertion Timing Waveform
rx_pma_ready
rx_reset_req (1)
rx_reset_ack
rx_aib_reset
rx_pmaif_reset
rx_rsfec_reset
rx_transfer_ready
Min 100 ns
Note:
1. If you have enabled the RS-FEC block, you must assert rx_reset_req after the tx_transfer_ready output is asserted.
6. Resetting Transceiver Channels
UG-20056 | 2019.02.04
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10 E-Tile Transceiver PHY User Guide
109

Intel Stratix 10 Specifications

General

Brand	Intel
Model	Stratix 10
Category	Control Unit
Language	English