Intel Stratix 10 User Manual

Figure 30. E-Tile Native PHY PLL Mode
Table 24. E-Tile Native PHY PLL Mode Options
Parameter Value Description
Number of reference clock
inputs
1, 2, 3, 4, 5 Specifies the desired number of reference clocks. The
Native PHY presents up to five clock inputs.
Initial TX reference clock
input selection
Based on the number of
reference clock input
Specifies the initially selected PLL reference clock input.
This indicates the starting clock input selection used for this
configuration when dynamically switching between multiple
TX reference clock inputs.
PLL output clock frequency TBD Specifies the PLL output frequency in units of MHz.
PLL output 2 clock
frequency
TBD Specifies the PLL output frequency for output 2 in units of
MHz.
PLL reference clock
frequency
Refer to the Intel Stratix 10
Device Datasheet.
Selects the reference clock frequency for the PLL.
2. Implementing the Transceiver PHY Layer in Intel Stratix 10 Devices
UG-20056 | 2019.02.04
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10 E-Tile Transceiver PHY User Guide
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Intel Stratix 10 Specifications

General

Brand	Intel
Model	Stratix 10
Category	Control Unit
Language	English