Intel Stratix 10 User Manual

Port Name Direction Width Description
tx_coreclkin
Input 1 bit for each
channel
Transfer clock between the FPGA core
and the transmitter
tx_coreclkin2
Input 1 bit for each
channel
2nd transfer clock between the FPGA
core and the transmitter
rx_clkout
Output 1 bit for each
channel
Clock output from the receiver. You can
select the full-rate, half-rate, or div66
option in the Native PHY GUI.
rx_clkout2
Output 1 bit for each
channel
2nd clock output from the receiver. You
can select the full-rate, half-rate, or
div66 option in the Native PHY GUI when
the port is enabled.
rx_coreclkin
Input 1 bit for each
channel
Transfer clock between the FPGA core
and the receiver
rsfec_avmm2_avmmread_in
Input 1 bit AVMM read signal of the AVMM2
interface for FEC. RS-FEC configurations
will be supported in a future release of
the Intel Quartus Prime software.
rsfec_avmm2_avmmrequest_in
Input 1 bit AVMM request signal of the AVMM2
interface for FEC. RS-FEC configurations
will be supported in a future release of
the Intel Quartus Prime software.
rsfec_avmm2_avmmwrite_in
Input 1 bit AVMM write signal of the AVMM2
interface for FEC. RS-FEC configurations
will be supported in a future release of
the Intel Quartus Prime software.
reconfig_clk
Input 1 bit Clock signal of reconfiguration interface
reconfig_reset
Input 1 bit Reset signal of reconfiguration interface
reconfig_write
Input 1 bit Write signal of reconfiguration interface
reconfig_read
Input 1 bit Read signal of reconfiguration interface
reconfig_address
Input 19 bit Address signal of reconfiguration
interface (the upper [n-1:19] address
bits of the reconfiguration address bus
specify the selected channel, where 'n' is
the log base 2 of the number of
channels)
reconfig_writedata
Input 8 bit Write data of reconfiguration interface
reconfig_readdata
Output 8 bit Read data of reconfiguration interface
reconfig_waitrequest
Output 1 bit Wait Request signal of reconfiguration
interface
Table 23. Parallel Data
E-Tile Native
PHY Mode
TX/RX PMA
Interface
Width
Enable TX/RX
double width
transfer
Valid Parallel Data Note
PMA Direct 16 No Data [15:0] N/A
PMA Direct 20 No Data [19:0] N/A
PMA Direct 32 No Data [31:0] N/A
PMA Direct 40 No Data [39:0] N/A
continued...
2. Implementing the Transceiver PHY Layer in Intel Stratix 10 Devices
UG-20056 | 2019.02.04
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Intel
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Stratix
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10 E-Tile Transceiver PHY User Guide
51

Intel Stratix 10 Specifications

General

Brand	Intel
Model	Stratix 10
Category	Control Unit
Language	English