Intel Stratix 10 User Manual

Port Name Direction Width Description
rx_ready
Output 1 bit for each
channel
Ready status signal of the receiver.
rx_is_lockedtodata
Output 1 bit for each
channel
Locked to data status signal of the
receiver.
rx_pma_elecidle
Input 1 bit for each
channel
Electrical Idle status signal of the
receiver PMA.
rx_fifo_empty
Output 1 bit for each
channel
Status signal indicating the receiver core
interface FIFO is empty.
rx_fifo_full
Output 1 bit for each
channel
Status signal indicating the receiver core
interface FIFO is full.
rx_fifo_pempty
Output 1 bit for each
channel
Status signal indicating the receiver core
interface FIFO is partially empty.
rx_fifo_pfull
Output 1 bit for each
channel
Status signal indicating the receiver core
interface FIFO is partially full.
rx_fifo_rd_en
Input 1 bit for each
channel
This port is used for Elastic FIFO mode.
Asserting this signal enables the read
from RX core FIFO.
tx_dll_lock
Output 1 bit for each
channel
TX DLL locked status signal for data
transfer
tx_fifo_empty
Output 1 bit for each
channel
Status signal indicating the transmitter
core interface FIFO is empty.
tx_fifo_full
Output 1 bit for each
channel
Status signal indicating the transmitter
core interface FIFO is full.
tx_fifo_pempty
Output 1 bit for each
channel
Status signal indicating the transmitter
core interface FIFO is partially empty.
tx_fifo_pfull
Output 1 bit for each
channel
Status signal indicating the transmitter
core interface FIFO is partially full.
latency_sclk
Input 1 bit for each
channel
Clock signal for latency measurement of
the deterministic latency application
rx_dl_async_pulse
Output 1 bit for each
channel
Asynchronous output pulse signal for the
receiver latency measurement of the
deterministic latency application. There
is a start pulse and a stop pulse.
rx_dl_measure_sel
Input 1 bit for each
channel
Mux select signal for the receiver latency
measurement. 1 is for the datapath
latency. 0 is for the wire delay.
tx_dl_async_pulse
Output 1 bit for each
channel
Asynchronous output pulse signal for the
transmitter latency measurement of the
deterministic latency application. There
is a start pulse and a stop pulse.
tx_dl_measure_sel
Input 1 bit for each
channel
Mux select signal for the transmitter
latency measurement. 1 is for the
datapath latency. 0 is for the wire delay.
tx_clkout
Output 1 bit for each
channel
Clock output from the transmitter. You
can select the full-rate, half-rate, or
div66 option in the Native PHY GUI.
tx_clkout2
Output 1 bit for each
channel
2nd clock output from the transmitter.
You can select the full-rate, half-rate, or
div66 option in the Native PHY GUI when
the port is enabled.
continued...
2. Implementing the Transceiver PHY Layer in Intel Stratix 10 Devices
UG-20056 | 2019.02.04
Intel
®
Stratix
®
10 E-Tile Transceiver PHY User Guide
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Intel Stratix 10 Specifications

General

Brand	Intel
Model	Stratix 10
Category	Control Unit
Language	English