Intel Stratix 10 User Manual

There are two mechanisms by which to facilitate bonding:
• Transceiver interface deskew logic
• Dedicated balanced transceiver reference clock tree
Once you enable bonding in the Native PHY IP core, both of these bonding
mechanisms are activated.
3.1.6.1. Transceiver Interface Deskew Logic
When you enable bonding in the Native PHY IP core, the deskew logic in the
transceiver interface aligns data transferred across multiple channels within the same
clock cycle.
Deskew logic requires your involvement. Bit-33 of the TX parallel data (data[33])
functions as the deskew pulse. (The bits used for the deskew depends on whether
double width mode is enabled and the PMA width. For single width transfer, Data[33]
and Data[113] are deskew bits (deskew pulse). For double width transfer, Data[33],
Data[73], Data[113], and Data[153] are deskew bits (deskew pulse).) You must drive
the deskew pulse bit of all the bonded channels with a pulse that is active on every
8th parallel clock cycle. The deskew logic uses the deskew pulse to align the FIFO.
Channel alignment requires several cycles to achieve alignment. You must perform
AVMM read to the TX deskew status register, cfg_tx_deskew_sts, of all the bonded
lanes to determine whether or not deskew is completed successfully. If it has, all the
bonded channels have aligned parallel data. The deskew status register also provides
further information for debugging if deskew is not successful.
cfg_tx_deskew_sts[2] - (0x09[4]):
• 0 = not aligned or not enabled or did't receive a deskew-bit
• 1 = aligned
cfg_tx_deskew_sts[1:0] - (0x09[3:2]):
• 00 = not yet received a deskew-bit
• 01 = not aligned
• 10 = received 1 set of aligned deskew-bits
• 11 = received 16 sets of aligned deskew-bits
The deskew mechanism runs continuously, so if the alignment lock is lost for some
reason, monitoring cfg_tx_deskew_sts informs you about the status. The deskew
mechanism works the same way for PMA direct high data rate PAM4 mode for two
EMIB channels. You must send the deskew pulses for the data you sent to two EMIBs
and at the master transceiver interface they are aligned to before being sent to a
single PMA.
3.1.6.2. Dedicated Balanced PLL Reference Clock Tree
Once bonding is enabled, use refclk0 on the hardware. This clock is connected to
the transceiver through a dedicated balanced clock tree. You do not need to do
anything on Native PHY side. You can select any reference clock; however, the fitter
checks that your selection on the reference clock number in the Native PHY is assigned
to refclk0 in the Intel Quartus Prime settings file (.qsf) assignments.
3. Intel Stratix 10 E-Tile Transceiver PHY Architecture
UG-20056 | 2019.02.04
Intel
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Stratix
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10 E-Tile Transceiver PHY User Guide
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Intel Stratix 10 Specifications

General

Brand	Intel
Model	Stratix 10
Category	Control Unit
Language	English