NXP Semiconductors UM11227 - Page 199

NXP Semiconductors
UM11227
NTM88 family of tire pressure monitor sensors
UM11227 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2020. All rights reserved.
User manual Rev. 6 — 24 April 2020
199 / 205
Tables
Tab. 1. Ordering information ..........................................2
Tab. 2. Device ID coding summary ............................... 3
Tab. 3. Example Exterior Marking ................................. 5
Tab. 4. Trace code definitions ....................................... 5
Tab. 5. Pin description ...................................................7
Tab. 6. CCR register field descriptions ........................13
Tab. 7. HCS08 instruction set summary ......................20
Tab. 8. Opcode map (Sheet 1 of 2) ............................ 29
Tab. 9. Opcode map (Sheet 2 of 2) ............................ 30
Tab. 10. BDC command summary ................................ 36
Tab. 11. BDC status and control register (BDCSCR) .... 38
Tab. 12. BDCSCR register field descriptions ................ 38
Tab. 13. System background debug force reset
register (SBDFR) .............................................40
Tab. 14. SBDFR register field description ..................... 40
Tab. 15. Register map description ................................ 40
Tab. 16. Register description format ............................. 47
Tab. 17. Interrupt service routines .................................50
Tab. 18. HFO frequency selections ...............................52
Tab. 19. Keyboard interrupt assignments ......................52
Tab. 20. STOP mode behavior ......................................55
Tab. 21. Memory map for parts delivered without
firmware in flash ..............................................58
Tab. 22. COP watchdog timeout period ........................ 61
Tab. 23. Truth table for pullup and pulldown resistors ... 64
Tab. 24. Port A data register (PTAD) (address $0000) .. 65
Tab. 25. PTAD register field descriptions ...................... 66
Tab. 26. Port A pin pull enable register (PTAPE)
(address $0001) .............................................. 66
Tab. 27. PTAPE register field descriptions ....................66
Tab. 28. Port A data direction register (PTADD)
(address $0003) .............................................. 66
Tab. 29. PTADD register field descriptions ................... 66
Tab. 30. Port B data register (PTBD) (address $0004) .. 67
Tab. 31. PTBD register field descriptions ...................... 67
Tab. 32. Port B pin pull enable register (PTBE)
(address $0005) .............................................. 67
Tab. 33. PTBE register field descriptions ...................... 67
Tab. 34. Port B data direction (PTBDD) (address
$0007) ............................................................. 67
Tab. 35. PTBDD register field descriptions ................... 68
Tab. 36. KBI status and control register (KBISC)
(address $000C) ............................................. 68
Tab. 37. KBISC register field descriptions .....................69
Tab. 38. Keyboard interrupt pin enable register
(KBIPE) (address $000D) ............................... 69
Tab. 39. KBIPE register field descriptions ..................... 69
Tab. 40. Keyboard interrupt edge select register
(KBIES) (address $000E) ................................69
Tab. 41. KBIES register field descriptions ..................... 70
Tab. 42. Ext. interrupt status and control register
(IRQSC) (address $000F) ............................... 70
Tab. 43. IRQSC register field descriptions .................... 70
Tab. 44. TPM1 clock source selection .......................... 72
Tab. 45. Timer status and control register (TPMSC)
(address $0010) .............................................. 73
Tab. 46. TPMSC register field descriptions ................... 73
Tab. 47. Timer counter high register (TPMCNTH)
(address $0011) .............................................. 74
Tab. 48. Timer counter low register (TPMCNTL)
(address $0012) .............................................. 74
Tab. 49. TPMCNTH/L register field descriptions ........... 75
Tab. 50. Timer modulo high register (TPMMODH)
(address $0013) .............................................. 75
Tab. 51. Timer modulo low register (TPMMODL)
(address $0014) .............................................. 75
Tab. 52. TPMMODH/L register field descriptions .......... 75
Tab. 53. Timer channel 0 status and control register
(TPMC0SC) (address $0015) ..........................75
Tab. 54. Timer channel 1 status and control register
(TPMC1SC) (address $0018) ..........................76
Tab. 55. TPMCySC register field descriptions ...............76
Tab. 56. Timer channel operating mode settings .......... 76
Tab. 57. Timer channel 0 value register (TPMC0VH)
(addresses $0016) .......................................... 77
Tab. 58. Timer channel 0 value register (TPMC0VL)
(addresses $0017) .......................................... 77
Tab. 59. Timer channel 1 value register (TPMC1VH)
(addresses $0019) .......................................... 77
Tab. 60. Timer channel 1 value register (TPMC1VL)
(addresses $001A) .......................................... 77
Tab. 61. TPMCyVH/L register field descriptions ............78
Tab. 62. Periodic wake-up status and control register
(PWUSR) (address $001B) ............................. 79
Tab. 63. PWUSR register field descriptions .................. 79
Tab. 64. Periodic wake-up divider register (PWUDIV)
(address $001C) ............................................. 80
Tab. 65. PWUDIV register field descriptions ................. 80
Tab. 66. Periodic wake-up interrupt register
(PWUCS0) (address $001D) ...........................80
Tab. 67. PWUCS0 register field descriptions ................ 80
Tab. 68. Periodic wake-up reset register (PWUCS1)
(address $001E) ..............................................81
Tab. 69. PWUCS1 register field descriptions ................ 81
Tab. 70. Periodic wake-up counter register (PWUS)
(address $001F) ..............................................81
Tab. 71. PWUS register field descriptions .....................81
Tab. 72. LF control 1 register (LFCTL1) (address
$0020) ............................................................. 92
Tab. 73. LFCTL1 register field descriptions ...................92
Tab. 74. LF control 2 register (LFCTL2) (address
$0021) ............................................................. 93
Tab. 75. LFCTL2 register field descriptions ...................93
Tab. 76. LF sampling time interval selection ................. 94
Tab. 77. LF sampling on time selection ........................ 94
Tab. 78. LF control 3 register (LFCTL3) (address
$0022) ............................................................. 94
Tab. 79. LFCTL3 register field descriptions ...................95
Tab. 80. LF carrier and data detect states .................... 95
Tab. 81. LF control 4 register (LFCTL4) (address
$0023) ............................................................. 96
Tab. 82. LFCTL4 register field descriptions ...................96