Xilinx SelectIO 7 Series - Page 154

154 www.xilinx.com 7 Series FPGAs SelectIO Resources User Guide
UG471 (v1.10) May 8, 2018
Chapter 3: Advanced SelectIO Logic Resources
• CLK and CLKB are driven by a BUFIO. OCLK and OCLKB are driven by a BUFIO that is
phase shifted by 90°. The two BUFIOs are driven from a single MMCM.
• CLK and CLKB are driven by a BUFG. OCLK and OCLKB are driven by a BUFG that is
phase shifted by 90°. The BUFGs are driven from a single MMCM. In either case, the
effective clocking is:
•CLK: 0°
• OCLK: 90°
• CLKB: 180°
• OCLKB: 270°
X-Ref Target - Figure 3-7
Figure 3-7: Logical View of ISERDESE2 Primitive in Oversample Mode
UG471_c3_07_021914
DDLY
CE2
CE1
CLKDIV
DYNCLKSEL
DYNCLKDIVSEL
SHIFTIN1
SHIFTIN2
RST
D
BITSLIP
OFB
CLK
REG
DQ
CLKB
REG
D
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
Q
REG
DQ
OCLKB
REG
DQ
REG
DQ
REG
DQ
REG
ISERDESE2
Primitive
DQ
REG
DQ
CLK
CLK
CLK
CLK
REG
Sample 1
DQ
Q1
Q2
Sample 2
Q3
SHIFTOUT1
SHIFTOUT2
O
Q4
Q5
Q6
Q7
Q8
REG
DQ
REG
DQ
REG
DQ
Sample 3
Sample 4
OCLK
Send Feedback